The asynchronous feedback loop on the err signal causes X to get stuck
on the sum signal when simulating. This change adds a check for
simulation only to force X to 0 so that unknown inputs get resolved
once the inputs are known.
Also added default values to the ports out and strobe_out, since having
them uninitialized and without reset was causing simulation issues in
other modules. The FPGA will initialize them to 0, so this change makes
the code equivalent to real hardware behavior.
Original-commit: b9f7af5807f73a5ac2612ea42ac2b65c26a3bff2
The always(*) block was never executing in some simulators because
there were no signals on the right-hand side in the block. Changing it
to an initial block ensures it always runs.
Original-commit: 0b965d579e2df962b91dac141eef6668f932e992
This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This
makes the naming consistent with the rest of the build process (which
uses "e310" for all variants of e31x) and fixes an issue in which the
wrong file name was used by rfnoc_image_builder.
Original-commit: bbd43b16e18ef0a0311ddf4635cbd29c4ac3c367
This updates the IO signatures so that all devices and RFNoC blocks use
the same IO signature for the DRAM. This is needed because the IO
signatures must match between the RFNoC blocks and the devices. This
means that some devices have extra bits in the IO signature for the
address, but the extra bits will simply be ignored.
Original-commit: 8f09caaa06725d2364c63ac7cff02f3298895f4a
- Adds test coverage for stream command and status packets
- Cleans up report output during simulation
- Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can
be run directly instead of just chdr_stream_endpoint_all_tb
Original-commit: 97cb396297828f57bba455a275966c58f1abce6e
This updates PkgChdrBfm to correct some errors when modeling stream
command and stream status packets.
- Fix behavior when CHDR_W = 512
- Fix assertions in read_ctrl()
Original-commit: ccf5d1e0a06bf8d46d7bf6dc33a17e3228a1bff4
This changes the behavior of the stream command with the INIT OpCode
such that sending the command with 0 for the values causes no flow
control stream status packets to be sent in response to incoming data.
Original-commit: 7c849afec4dad605ff6f32f7319933f99a4cd1ce
Fixes various synthesis/simulation warnings that were being generated
due to incorrectly sized constants.
Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.
Original-commit: 9c4a23f0a2a2d38ace75e4ab29f6f62f64155d81
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.
Original-commit: e94a209c5b2559348593a6732d694fd49ab59ad0
Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.
Original-commit: 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67
Device was set to e31x, but this is not a valid device type. All e31x
devices use the e310 device type.
Original-commit: 60b76ebb31f9d1672c1b18367346b3fb522e13e9
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.
Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
Thange allows the mux to switch cleanly between packets, if the mux
select input is changed while a packet is in flight.
Original-commit: cee09d96aee51795ba2c6578f75f25f30ea11548
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.
Also cleans up trailing white space.
Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1
The max FFT size was 4096, but we don't currently have any devices that
can do that without modification. This is because, currently, the FFT
size must be the same as the packet size, and the largest packet
size supported by most devices is about 8000 bytes, or 2000
sc16 samples. Therefore, the largest FFT size supported without
modifying other code is 1024 samples.
This change frees up about 21% of the LUTs and 36% of the BRAM used by
axi_fft and makes the software block controller and the IP agree on the
maximum FFT size.
Original-commit: 4f387c8ff0571deedc86dc459e94e555b9768282
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.
Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
Adding a check for bursts that cross the 4 KiB boundary to the AXI4
memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
Original-commit: 24f8bb39fd2769ff93d11b21152a834500152de4
This change fixes the case where CHDR_W < ITEM_W*NIPC.
It also adds a state machine to stall the input to the pyld_fifo to
ensure that the pkt_info_fifo will not overflow. Previously in some
cases it allowed the same word to be inserted into the pyld_fifo
multiple times.
Original-commit: b862eda69cf41c7044a1805324f2fcfef5b0ba3d
This module takes an AXI-Stream without TLAST and outputs the
same AXI-Stream with TLAST based on the provided packet size
input.
Original-commit: b0b3849a18e1f2d3cb255a507b01ac5e7a9416a0
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
Add DEFAULT_M and DEFAULT_N parameters for rate changing cores.
This allows the host to not need to configure fixed rate change
cores.
Original-commit: 983fad664436301c31c3bc8c81b538a41537598b
This change allows detection of attempting to execute setupenv.sh
rather than sourcing it, which is required.
Original-commit: 6faec1d4a14a1af52681aabf19c9040dcee772ff
This adds support for colored output and support for directories added
to the list of source files (for HLS support).
Original-commit: 5b3d66e5b7cedb7098de3e4dbbee70af04a3626e
For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.
Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a
The address ranges configured for the AXI interconnect IP limited the
amount of accessible DRAM to two 32 MB regions. This change makes the
full 1G available to all DRAM ports.
Original-commit: bba0cddfadcb744e8a6fae27d57ba8d3995eaf64
This updates the chdr_to_axis method so that it doesn't change the
input chdr_packet object. This is useful in case there are other
references to that object in use. Not modifying the object means that
you don't always have to copy the object before passing it to this
method.
Original-commit: 259506c4993834d9ef8ccb48635623552b075237
The axis_data_to_chdr block previously only sampled the sideband
information at the end of the packet. This adds a parameter that
controls if the sideband information should be sampled at the beginning
of the packet or the end of the packet. In the former case, large
internal packet buffers are not required.
Original-commit: a8c4f021277cf3b0a0897fa9da0252541512f3a6
Add -voptargs=+acc to the default options when running vsim. This
option enables debug command access to objects in the design, which is
generally needed for debugging in the GUI.
Original-commit: eed2d2348cab7dc786673f0649373809d04027d5
The axis_split module takes a single AXI-Stream input and duplicates it
onto multiple AXI-Stream outputs. This block correctly handles the
somewhat tricky flow-control logic so that the AXI-Stream handshake
protocol is honored at all top-level ports.
Original-commit: fa0f4b2833119d57d331f592028ff9f032895c89
Xilinx changed the way [all_registers -edge_triggered] is treated such
that set_max_delay constraints that use it can cause segmentation and
cause clocks to not be propagated to all endpoints. Changing to
[all_ffs] avoids this potential issue.
Original-commit: 55e422535292c29de00b80f15b0a49ca3fb94f26
Xilinx changed the default Vivado install location from /opt/Xilix to
/tools/Xilinx. This commit adds support for finding Vivado in either
the new location or the old location.
Original-commit: 156d714b8fb288100d242ea200ae1d1dcd6bcd57
This adds the "modelsim" simulator option to run_testbenches.py to allow
for regression testing of the native ModelSim simulation target.
Original-commit: 39d6007ca7e3b27e8230db6690faa7469ca62cb2
For example, the ChdrPacket typedef is being renamed from ChdrPacket to
ChdrPacket_t. This allows the code to distinguish between the
unparameterized class and the already parameterized class. This isn't
strictly necessary, but it makes some Vivado 2019.1 bugs easier to work
around. It also makes the code slightly less ambiguous.
Original-commit: df27e9fa05d2d767f69182763852f6803c5b2a34
This adds variants of the send and recv methods in RfnocBlockCtrlBfm
and ChdrIfaceBfm that input/output items instead of CHDR words.
Original-commit: aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6
This replaces chdr_word_t, which was a statically defined 64-bit data
type, with a paramaterizable data type that matches the defined CHDR_W.
Code that formerly referenced the chdr_word_t data type can now define
the data type for their desired CHDR_W and ITEM_W as follows:
// Define the CHDR word and item/sample data types
typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t;
ITEM_W is optional when defining chdr_word_t if items are not
needed. Static methods in the ChdrData class also provide the ability to
convert between CHDR words and data items. For example:
// Convert CHDR data buffer to a buffer of samples
samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
Original-commit: fc895feacb8dde3b02c9a4eccb4b4f4a654f2881
This eliminates the complicated semaphore from the testbench and brings
the radio testbench in line with the other testbenches.
Original-commit: 8727642de2aa22e982e012d85d32325f664a3e9e
Wade Fife