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Wade Fife 34d68cf4ca fpga: rfnoc: Add option to sample sideband info at start of packet 
The axis_data_to_chdr block previously only sampled the sideband
information at the end of the packet. This adds a parameter that
controls if the sideband information should be sampled at the beginning
of the packet or the end of the packet. In the former case, large
internal packet buffers are not required.


Original-commit: a8c4f021277cf3b0a0897fa9da0252541512f3a6
2020-04-14 16:37:43 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: rfnoc: Add option to sample sideband info at start of packet
2020-04-14 16:37:43 -05:00
sim
fpga: sim: Export ChdrPacket in PkgRfnoBlockCtrlBfm
2020-04-14 16:37:43 -05:00
tools
fpga: tools: Add -voptargs=+acc to ModelSim GUI
2020-04-14 16:37:43 -05:00
top
fpga: e31x: Update constraints to avoid timing issues
2020-04-08 17:24:15 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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