Wade Fife 2487e7bdf8 fpga: e31x: Update constraints to avoid timing issues ...

Xilinx changed the way [all_registers -edge_triggered] is treated such
that set_max_delay constraints that use it can cause segmentation and
cause clocks to not be propagated to all endpoints. Changing to
[all_ffs] avoids this potential issue.


Original-commit: 55e422535292c29de00b80f15b0a49ca3fb94f26

2020-04-08 17:24:15 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Add gate to dynamically enable control-port interfaces

2020-04-01 11:02:16 -05:00

sim

sim: Rename class typedefs

2020-03-09 13:43:05 -05:00

tools

fpga: tools: Add support for .sdc in Vivado

2020-04-02 08:13:35 -05:00

top

fpga: e31x: Update constraints to avoid timing issues

2020-04-08 17:24:15 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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