b210-k7-fpga

T

Wade Fife 98463e99d0 fpga: tools: Add contents of directories for HDL source

For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.


Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a

2020-05-26 13:36:55 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Add Vector IIR RFNoC block

2020-05-19 14:22:55 -05:00

sim

fpga: sim: Don't affect packet arguments in chdr_to_axis

2020-05-04 23:40:25 -05:00

tools

fpga: tools: Add contents of directories for HDL source