Wade Fife 98463e99d0 fpga: tools: Add contents of directories for HDL source ...

For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.


Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a

2020-05-26 13:36:55 -05:00

..

make

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

scripts

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

utils

fpga: tools: Add ModelSim to run_testbenches.py

2020-03-23 18:01:53 -05:00