miegl/b210-k7-fpga
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b210-k7-fpga/tools/scripts
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Wade Fife 98463e99d0 fpga: tools: Add contents of directories for HDL source 
For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.


Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a
2020-05-26 13:36:55 -05:00
..
check_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
git-hash.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ise_jtag_program.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
launch_vivado.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
launch_vivado.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
setupenv_base.sh
fpga: tools: Option to check for full Vivado version
2020-04-14 10:43:51 -05:00
shared-ip-loc-manage.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_check_syntax.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_gen_ip_makefile.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_gen_part_id.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_bd.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_hls_ip.tcl
fpga: tools: Fix HLS IP build with Cygwin
2020-05-12 13:47:20 -05:00
viv_generate_ip.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_hardware_utils.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_ip_utils.tcl
fpga: tools: Ignore BD layout info for TCL-based BD
2020-03-12 10:33:24 -05:00
viv_ip_xci_editor.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_sim_project.tcl
fpga: tools: Add contents of directories for HDL source
2020-05-26 13:36:55 -05:00
viv_strategies.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_synth.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_utils.tcl
fpga: tools: Add contents of directories for HDL source
2020-05-26 13:36:55 -05:00
xil_bitfile_parser.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00