fpga: lib: Add axis_packetize module
This module takes an AXI-Stream without TLAST and outputs the same AXI-Stream with TLAST based on the provided packet size input. Original-commit: b0b3849a18e1f2d3cb255a507b01ac5e7a9416a0
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
parent
0c67c21d6c
commit
3e1e0be3bc
@@ -34,4 +34,5 @@ axis_upsizer.v \
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axis_downsizer.v \
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axis_width_conv.v \
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axis_split.v \
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axis_packetize.v \
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))
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@@ -0,0 +1,161 @@
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//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_packetize
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//
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// Description:
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//
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// This module takes in an axi_stream without packet boundaries (i.e.,
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// without tlast) and groups the data into packets by adding tlast at the
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// appropriate time. The size of the packet is controlled by the "size"
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// input, which is sampled at the beginning of each packet to be output. The
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// packet_size input indicates the number of i_tdata words to group into a
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// packet. The i_tlength output indicates the length of the packet being
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// output.
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//
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// The gate input causes data transfers to be stopped at the end of the
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// current packet when the gate input is asserted. It is not legal to
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// deassert tvalid once it has been asserted until the next transfer is
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// completed, so this module monitors the state of the AXI-Stream protocol
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// so that no protocol violations occur.
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//
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// Note that the current transfer may still complete after gate has been
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// asserted, so the downstream logic must be able to account for at least
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// one more transfer.
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//
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// Parameters:
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//
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// DATA_W : Width of the tdata signals.
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// SIZE_W : The width of the packet size port. This dictates the
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// maximum packet size.
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// FLUSH : Controls whether or not the input should be stalled or
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// flushed. That is, when FLUSH=0, the input data is stalled
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// whenever the gate is on (i_tready becomes 0). When
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// FLUSH=1, the input data is dropped whenever the gate is on
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// (i_tready becomes 1).
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// DEFAULT_SIZE : The default packet size to use, if it doesn't need to be
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// changed at run time.
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//
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module axis_packetize #(
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parameter DATA_W = 32,
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parameter SIZE_W = 16,
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parameter FLUSH = 0,
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parameter DEFAULT_SIZE = 2**SIZE_W-1
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) (
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input wire clk,
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input wire rst,
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input wire gate, // Stop or "gate" packet output
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input wire [SIZE_W-1:0] size, // Size to use for the next packet
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// Input data stream
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input wire [DATA_W-1:0] i_tdata,
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input wire i_tvalid,
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output wire i_tready,
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// Output data stream
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output wire [DATA_W-1:0] o_tdata,
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output reg o_tlast,
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output wire o_tvalid,
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input wire o_tready,
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output wire [SIZE_W-1:0] o_tuser // Current packet's size
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);
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reg start_of_packet = 1; // Next sample is start of a packet
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reg [SIZE_W-1:0] word_count = 0; // Count of output words
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reg [SIZE_W-1:0] current_size = DEFAULT_SIZE; // Current packet size
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reg gating = 1'b1; // Indicate if output is blocked
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reg mid_packet = 1'b0; // Indicate if we're in the middle of a packet
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//---------------------------------------------------------------------------
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// Packet Size Logic
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//---------------------------------------------------------------------------
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assign o_tuser = current_size;
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always @(posedge clk) begin
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if (rst) begin
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start_of_packet <= 1;
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word_count <= 0;
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current_size <= DEFAULT_SIZE;
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o_tlast <= 0;
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end else begin
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if (gating) begin
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// Wait until we're enabled. Setup for the start of the next packet.
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start_of_packet <= 1;
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current_size <= size;
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word_count <= 0;
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o_tlast <= (size == 1);
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end else if (o_tvalid && o_tready) begin
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start_of_packet <= 1'b0;
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word_count <= word_count + 1;
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if (o_tlast) begin
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// This is the last sample, so restart everything for a new packet.
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o_tlast <= (size == 1);
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current_size <= size;
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word_count <= 0;
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start_of_packet <= 1'b1;
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end else if (word_count == current_size-2) begin
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// This is the second to last sample, so we assert tlast for the
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// last sample.
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o_tlast <= 1'b1;
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end
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end else if (start_of_packet) begin
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// We're waiting for the start of the next packet. Keep checking the
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// size input until the next packet starts.
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current_size <= size;
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word_count <= 0;
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o_tlast <= (size == 1);
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end
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end
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end
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//---------------------------------------------------------------------------
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// Handshake Monitor
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//---------------------------------------------------------------------------
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// We start out gated to allow a clock cycle for the length to be loaded.
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// Monitor the state of the handshake so we know when it's OK to
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// enable/disable data transfer.
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always @(posedge clk) begin
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if (rst) begin
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gating = 1'b1;
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mid_packet = 1'b0;
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end else begin
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// Keep track of if we are in the middle of a packet or not. Note that
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// mid_packet will be 0 for the first transfer of a packet.
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if (o_tvalid && o_tready) begin
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if (o_tlast) begin
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mid_packet = 1'b0;
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end else begin
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mid_packet = 1'b1;
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end
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end
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if (gating) begin
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// We can stop gating any time
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if (!gate) gating <= 0;
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end else begin
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// Only start gating between packets or at the end of a packet
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if ((mid_packet && !o_tvalid) || (o_tvalid && o_tready && o_tlast)) begin
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gating <= gate;
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end
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end
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end
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end
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//---------------------------------------------------------------------------
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// Data Pass-Through
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//---------------------------------------------------------------------------
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assign o_tdata = i_tdata;
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assign o_tvalid = i_tvalid && !gating;
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assign i_tready = FLUSH ? (o_tready || gating) : (o_tready && !gating);
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endmodule
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