Wade Fife 6940db90e3 fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tb ...

Original-commit: 8661f46df66329511ccb3cf083830e19d65ea402

2020-06-25 14:44:04 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tb

2020-06-25 14:44:04 -05:00

sim

fpga: lib: Add interface and model for AXI4-Lite

2020-06-24 09:56:31 -05:00

tools

fpga: tools: Fix ModelSim return status

2020-06-18 15:26:07 -05:00

top

fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin

2020-06-12 15:50:16 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%