Wade Fife 5f792ad48e fpga: tools: Highlight suppressible errors from vlint ...

Original-commit: 5244c06ae71589a08f337371d91798a6ac3d292b

2020-06-29 13:41:15 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Fix axi_packet_gate RAM dib width

2020-06-29 13:41:15 -05:00

sim

fpga: lib: Add synthesizable AXI4-Stream SV components

2020-06-25 14:44:04 -05:00

tools

fpga: tools: Highlight suppressible errors from vlint

2020-06-29 13:41:15 -05:00

top

fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin

2020-06-12 15:50:16 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%