fpga: lib: Fix axi_packet_gate RAM dib width

Original-commit: ed1b58053c53bfbd3f3b667a0ebe0aa8066e2b0e
2020-06-29 13:41:15 -05:00
parent 9b0e42678f
commit 9e0f859bb6
1 changed files with 1 additions and 1 deletions
@@ -70,7 +70,7 @@ module axi_packet_gate #(
    .clka (clk), .ena(1'b1), .wea(wr_en),
    .addra(wr_addr), .dia(wr_data), .doa(),
    .clkb (clk), .enb(rd_en), .web(1'b0),
-    .addrb(rd_addr), .dib({WIDTH{1'b0}}), .dob(rd_data)
+    .addrb(rd_addr), .dib({WIDTH+1{1'b0}}), .dob(rd_data)
  );

  // FIFO empty/full logic. The condition for both