Wade Fife d6849765ec fpga: sim: chdr_stream_endpoint_tb improvements ...

- Adds test coverage for stream command and status packets
- Cleans up report output during simulation
- Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can
  be run directly instead of just chdr_stream_endpoint_all_tb


Original-commit: 97cb396297828f57bba455a275966c58f1abce6e

2020-08-31 08:16:43 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: sim: chdr_stream_endpoint_tb improvements

2020-08-31 08:16:43 -05:00

sim

fpga: sim: Fix stream command and status models

2020-08-31 08:16:43 -05:00

tools

fpga: rfnoc: Remove deprecated files

2020-08-23 13:52:26 -05:00

top

fpga: n3xx: Update AXI interconnect address range

2020-08-28 15:07:38 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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