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fpga: n3xx: Update AXI interconnect address range

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This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: c6bb9924e56664ccb337694f8ef485ba8245edfd
This commit is contained in:
Wade Fife
2020-08-28 15:07:38 -05:00
parent 7e3f04d0ab
commit bd5d539bc2
4 changed files with 2217 additions and 2928 deletions
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top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd
+839 -715
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top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml
+5 -18
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@@ -1,18 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="33">
<Root MajorVersion="0" MinorVersion="37">
<CompositeFile CompositeFileTopName="axi_intercon_2x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1501543653"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1501543653"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1501543653"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1591253143"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1591253143"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1591253143"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1591253143"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/axi_intercon_2x64_256_bd_s00_cc_0/axi_intercon_2x64_256_bd_s00_cc_0.xci" Type="IP">
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_256_bd_m00_rs_0/axi_intercon_2x64_256_bd_m00_rs_0.xci" Type="IP">
<Instance HierarchyPath="m00_rs"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
@@ -77,13 +71,6 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/axi_intercon_2x64_256_bd_s01_cc_0/axi_intercon_2x64_256_bd_s01_cc_0.xci" Type="IP">
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
</FileCollection>
</CompositeFile>
</Root>
top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd
+1368 -2191
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top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml
+5 -4
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@@ -1,10 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="33">
<Root MajorVersion="0" MinorVersion="37">
<CompositeFile CompositeFileTopName="axi_intercon_4x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1501543653"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1501543653"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1501543653"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1591253143"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1591253143"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1591253143"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1591253143"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/axi_intercon_4x64_256_bd_m00_rs_0/axi_intercon_4x64_256_bd_m00_rs_0.xci" Type="IP">
<Instance HierarchyPath="m00_rs"/>