miegl/b210-k7-fpga
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Wade Fife bd5d539bc2 fpga: n3xx: Update AXI interconnect address range 
This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: c6bb9924e56664ccb337694f8ef485ba8245edfd
2020-08-28 15:07:38 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: rfnoc: Update CHDR stream INIT command
2020-08-28 15:02:41 -05:00
sim
fpga: sim: Update PkgEthernet
2020-07-31 13:22:29 -05:00
tools
fpga: rfnoc: Remove deprecated files
2020-08-23 13:52:26 -05:00
top
fpga: n3xx: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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