diff --git a/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd b/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd
index 1218295..c2249e1 100644
--- a/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd
+++ b/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd
@@ -1,715 +1,839 @@
-
-
-
-
- xilinx.com
- BlockDiagram
- axi_intercon_2x64_256_bd
- 1.00.a
-
-
- isTop
- true
-
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-
-
- M00_AXI
-
-
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- NUM_WRITE_OUTSTANDING
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-
-
-
-
- S00_AXI
-
-
-
-
-
- DATA_WIDTH
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-
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- NUM_WRITE_OUTSTANDING
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- MAX_BURST_LENGTH
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- PHASE
- 0.000
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-
- S01_AXI
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-
-
-
-
- DATA_WIDTH
- 64
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- PROTOCOL
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- FREQ_HZ
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- HAS_QOS
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- HAS_REGION
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- HAS_WSTRB
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-
- HAS_BRESP
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-
- HAS_RRESP
- 1
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-
- SUPPORTS_NARROW_BURST
- 1
-
-
- NUM_READ_OUTSTANDING
- 2
-
-
- NUM_WRITE_OUTSTANDING
- 2
-
-
- MAX_BURST_LENGTH
- 256
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-
- PHASE
- 0.000
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- CLK.M00_AXI_ACLK
- Clk
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- CLK
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- M00_AXI_ACLK
-
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- CLK_DOMAIN
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-
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- ASSOCIATED_RESET
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- CLK
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- S00_AXI_ACLK
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- FREQ_HZ
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-
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- ASSOCIATED_RESET
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-
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-
- RST.S00_AXI_ARESETN
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- CLK
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- S01_AXI_ACLK
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- CLK_DOMAIN
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-
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- ASSOCIATED_RESET
- S01_AXI_ARESETN
-
-
-
-
- RST.S01_AXI_ARESETN
- Reset
- Reset
-
-
-
-
-
-
- RST
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- S01_AXI_ARESETN
-
-
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- BlockDiagram
- :vivado.xilinx.com:
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- M00_AXI_ACLK
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- in
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- M00_AXI_ARESETN
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- in
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- S00_AXI_ACLK
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- S00_AXI_ARESETN
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- S01_AXI_ACLK
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- in
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- S01_AXI_ARESETN
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- S00_AXI
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- S01_AXI
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- SEG_M00_AXI_Reg
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- M00_AXI
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- Reg
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- 64K
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- register
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- xilinx.com
- BlockDiagram
- axi_intercon_2x64_256_bd_imp
- 1.00.a
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-
- m00_rs
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- axi_intercon_2x64_256_bd_m00_rs_0
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- s00_rs
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- s00_width_conv
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- axi_intercon_2x64_256_bd_s00_width_conv_0
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- s01_rs
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- axi_intercon_2x64_256_bd_s01_rs_0
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- s01_width_conv
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- axi_intercon_2x64_256_bd_s01_width_conv_0
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- s01_rs_256
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- axi_intercon_2x64_256_bd_s01_rs_256_0
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+{
+ "design": {
+ "design_info": {
+ "boundary_crc": "0x2ACC76BCF1A32A09",
+ "device": "xc7z100ffg900-2",
+ "name": "axi_intercon_2x64_256_bd",
+ "synth_flow_mode": "None",
+ "tool_version": "2019.1.1_AR73068",
+ "validated": "true"
+ },
+ "design_tree": {
+ "m00_rs": "",
+ "s00_rs": "",
+ "s00_width_conv": "",
+ "s01_rs": "",
+ "s01_width_conv": "",
+ "xbar": "",
+ "s01_rs_256": "",
+ "s00_rs_256": ""
+ },
+ "interface_ports": {
+ "M00_AXI": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+ "parameters": {
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+ "value": "32"
+ },
+ "ARUSER_WIDTH": {
+ "value": "0",
+ "value_src": "ip_prop"
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+ "value_src": "ip_prop"
+ },
+ "BUSER_WIDTH": {
+ "value": "0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_2x64_128_bd_M00_ACLK"
+ },
+ "DATA_WIDTH": {
+ "value": "256"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "default"
+ },
+ "HAS_BRESP": {
+ "value": "1",
+ "value_src": "const_prop"
+ },
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+ "value": "1",
+ "value_src": "default"
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+ "value": "1",
+ "value_src": "default"
+ },
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+ "value": "1",
+ "value_src": "default"
+ },
+ "HAS_PROT": {
+ "value": "1",
+ "value_src": "const_prop"
+ },
+ "HAS_QOS": {
+ "value": "1",
+ "value_src": "default"
+ },
+ "HAS_REGION": {
+ "value": "1",
+ "value_src": "default"
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+ "HAS_RRESP": {
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+ "value_src": "default"
+ },
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+ "value": "1",
+ "value_src": "const_prop"
+ },
+ "ID_WIDTH": {
+ "value": "1",
+ "value_src": "ip_prop"
+ },
+ "INSERT_VIP": {
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+ "value_src": "default"
+ },
+ "MAX_BURST_LENGTH": {
+ "value": "256",
+ "value_src": "ip_prop"
+ },
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+ "value": "2"
+ },
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+ "value_src": "ip_prop"
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+ "value_src": "ip_prop"
+ },
+ "WUSER_WIDTH": {
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+ "value_src": "ip_prop"
+ }
+ }
+ },
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+ "ARUSER_WIDTH": {
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+ },
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+ "value": "64"
+ },
+ "FREQ_HZ": {
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+ },
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+ },
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+ },
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+ "PHASE": {
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+ },
+ "PROTOCOL": {
+ "value": "AXI4"
+ },
+ "READ_WRITE_MODE": {
+ "value": "READ_WRITE"
+ },
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+ },
+ "RUSER_WIDTH": {
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+ "value": "1"
+ },
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+ },
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+ }
+ }
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+ "S01_AXI": {
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+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+ "parameters": {
+ "ADDR_WIDTH": {
+ "value": "32"
+ },
+ "ARUSER_WIDTH": {
+ "value": "0"
+ },
+ "AWUSER_WIDTH": {
+ "value": "0"
+ },
+ "BUSER_WIDTH": {
+ "value": "0"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_2x64_128_bd_S01_ACLK"
+ },
+ "DATA_WIDTH": {
+ "value": "64"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "default"
+ },
+ "HAS_BRESP": {
+ "value": "1"
+ },
+ "HAS_BURST": {
+ "value": "1"
+ },
+ "HAS_CACHE": {
+ "value": "1"
+ },
+ "HAS_LOCK": {
+ "value": "1"
+ },
+ "HAS_PROT": {
+ "value": "1"
+ },
+ "HAS_QOS": {
+ "value": "1"
+ },
+ "HAS_REGION": {
+ "value": "1"
+ },
+ "HAS_RRESP": {
+ "value": "1"
+ },
+ "HAS_WSTRB": {
+ "value": "1"
+ },
+ "ID_WIDTH": {
+ "value": "1"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "MAX_BURST_LENGTH": {
+ "value": "256"
+ },
+ "NUM_READ_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_READ_THREADS": {
+ "value": "1"
+ },
+ "NUM_WRITE_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_WRITE_THREADS": {
+ "value": "1"
+ },
+ "PHASE": {
+ "value": "0.000"
+ },
+ "PROTOCOL": {
+ "value": "AXI4"
+ },
+ "READ_WRITE_MODE": {
+ "value": "READ_WRITE"
+ },
+ "RUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "RUSER_WIDTH": {
+ "value": "0"
+ },
+ "SUPPORTS_NARROW_BURST": {
+ "value": "1"
+ },
+ "WUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "WUSER_WIDTH": {
+ "value": "0"
+ }
+ }
+ }
+ },
+ "ports": {
+ "M00_AXI_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "M00_AXI",
+ "value_src": "default"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "M00_AXI_ARESETN"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_2x64_128_bd_M00_ACLK"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "default"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ }
+ }
+ },
+ "M00_AXI_ARESETN": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "default"
+ }
+ }
+ },
+ "S00_AXI_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "S00_AXI",
+ "value_src": "default"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "S00_AXI_ARESETN"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_2x64_128_bd_S00_ACLK"
+ },
+ "FREQ_HZ": {
+ "value": "1000000000"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ }
+ }
+ },
+ "S00_AXI_ARESETN": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "default"
+ }
+ }
+ },
+ "S01_AXI_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "S01_AXI",
+ "value_src": "default"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "S01_AXI_ARESETN"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_2x64_128_bd_S01_ACLK"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "default"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ }
+ }
+ },
+ "S01_AXI_ARESETN": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "default"
+ }
+ }
+ }
+ },
+ "components": {
+ "m00_rs": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_2x64_256_bd_m00_rs_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ }
+ }
+ },
+ "s00_rs": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_2x64_256_bd_s00_rs_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
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\ No newline at end of file
diff --git a/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml b/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml
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- 0.000
-
-
-
-
-
-
-
- CLK_DOMAIN
- axi_intercon_4x64_128_bd_S00_ACLK
-
-
-
-
-
-
-
-
-
- CLK.M00_AXI_ACLK
- Clk
- Clock
-
-
-
-
-
-
- CLK
-
-
- M00_AXI_ACLK
-
-
-
-
-
- FREQ_HZ
- 200000000
-
-
-
-
-
-
-
- PHASE
- 0.000
-
-
-
-
-
-
-
- CLK_DOMAIN
- axi_intercon_4x64_128_bd_M00_ACLK
-
-
-
-
-
-
-
- ASSOCIATED_BUSIF
- M00_AXI
-
-
-
-
-
-
-
- ASSOCIATED_RESET
- M00_AXI_ARESETN
-
-
-
-
-
-
-
-
-
- RST.M00_AXI_ARESETN
- Reset
- Reset
-
-
-
-
-
-
- RST
-
-
- M00_AXI_ARESETN
-
-
-
-
-
- POLARITY
- ACTIVE_LOW
-
-
-
-
-
-
-
-
-
- CLK.S00_AXI_ACLK
- Clk
- Clock
-
-
-
-
-
-
- CLK
-
-
- S00_AXI_ACLK
-
-
-
-
-
- FREQ_HZ
- 350000000
-
-
-
-
-
-
-
- PHASE
- 0.000
-
-
-
-
-
-
-
- CLK_DOMAIN
- axi_intercon_4x64_128_bd_S00_ACLK
-
-
-
-
-
-
-
- ASSOCIATED_BUSIF
- S00_AXI
-
-
-
-
-
-
-
- ASSOCIATED_RESET
- S00_AXI_ARESETN
-
-
-
-
-
-
-
-
-
- RST.S00_AXI_ARESETN
- Reset
- Reset
-
-
-
-
-
-
- RST
-
-
- S00_AXI_ARESETN
-
-
-
-
-
- POLARITY
- ACTIVE_LOW
-
-
-
-
-
-
-
-
-
- CLK.S01_AXI_ACLK
- Clk
- Clock
-
-
-
-
-
-
- CLK
-
-
- S01_AXI_ACLK
-
-
-
-
-
- FREQ_HZ
- 350000000
-
-
-
-
-
-
-
- PHASE
- 0.000
-
-
-
-
-
-
-
- CLK_DOMAIN
- axi_intercon_4x64_128_bd_S01_ACLK
-
-
-
-
-
-
-
- ASSOCIATED_BUSIF
- S01_AXI
-
-
-
-
-
-
-
- ASSOCIATED_RESET
- S01_AXI_ARESETN
-
-
-
-
-
-
-
-
-
- RST.S01_AXI_ARESETN
- Reset
- Reset
-
-
-
-
-
-
- RST
-
-
- S01_AXI_ARESETN
-
-
-
-
-
- POLARITY
- ACTIVE_LOW
-
-
-
-
-
-
-
-
-
- CLK.S02_AXI_ACLK
- Clk
- Clock
-
-
-
-
-
-
- CLK
-
-
- S02_AXI_ACLK
-
-
-
-
-
- FREQ_HZ
- 350000000
-
-
-
-
-
-
-
- PHASE
- 0.000
-
-
-
-
-
-
-
- CLK_DOMAIN
- axi_intercon_4x64_128_bd_S00_ACLK
-
-
-
-
-
-
-
- ASSOCIATED_BUSIF
- S02_AXI
-
-
-
-
-
-
-
- ASSOCIATED_RESET
- S00_AXI_ARESETN:S02_AXI_ARESETN
-
-
-
-
-
-
-
-
-
- RST.S02_AXI_ARESETN
- Reset
- Reset
-
-
-
-
-
-
- RST
-
-
- S02_AXI_ARESETN
-
-
-
-
-
- POLARITY
- ACTIVE_LOW
-
-
-
-
-
-
-
-
-
- CLK.S03_AXI_ACLK
- Clk
- Clock
-
-
-
-
-
-
- CLK
-
-
- S03_AXI_ACLK
-
-
-
-
-
- FREQ_HZ
- 350000000
-
-
-
-
-
-
-
- PHASE
- 0.000
-
-
-
-
-
-
-
- CLK_DOMAIN
- axi_intercon_4x64_128_bd_S00_ACLK
-
-
-
-
-
-
-
- ASSOCIATED_BUSIF
- S02_AXI:S03_AXI
-
-
-
-
-
-
-
- ASSOCIATED_RESET
- S00_AXI_ARESETN:S02_AXI_ARESETN:S03_AXI_ARESETN
-
-
-
-
-
-
-
-
-
- RST.S03_AXI_ARESETN
- Reset
- Reset
-
-
-
-
-
-
- RST
-
-
- S03_AXI_ARESETN
-
-
-
-
-
- POLARITY
- ACTIVE_LOW
-
-
-
-
-
-
-
-
-
-
-
-
- BlockDiagram
- :vivado.xilinx.com:
-
-
-
-
-
- M00_AXI_ACLK
-
- in
-
-
-
- M00_AXI_ARESETN
-
- in
-
-
-
- S00_AXI_ACLK
-
- in
-
-
-
- S00_AXI_ARESETN
-
- in
-
-
-
- S01_AXI_ACLK
-
- in
-
-
-
- S01_AXI_ARESETN
-
- in
-
-
-
- S02_AXI_ACLK
-
- in
-
-
-
- S02_AXI_ARESETN
-
- in
-
-
-
- S03_AXI_ACLK
-
- in
-
-
-
- S03_AXI_ARESETN
-
- in
-
-
-
-
-
-
- S00_AXI
- 4G
- 32
-
-
- SEG_M00_AXI_Reg
- /M00_AXI/Reg
- 0x00000000
- 1G
-
-
-
-
- S01_AXI
- 4G
- 32
-
-
- SEG_M00_AXI_Reg
- /M00_AXI/Reg
- 0x00000000
- 1G
-
-
-
-
- S02_AXI
- 4G
- 32
-
-
- SEG_M00_AXI_Reg
- /M00_AXI/Reg
- 0x00000000
- 1G
-
-
-
-
- S03_AXI
- 4G
- 32
-
-
- SEG_M00_AXI_Reg
- /M00_AXI/Reg
- 0x00000000
- 1G
-
-
-
-
-
-
- M00_AXI
-
- Reg
- 0
- 64K
- 32
- register
-
-
-
-
-
-
- xilinx.com
- BlockDiagram
- axi_intercon_4x64_256_bd_imp
- 1.00.a
-
-
- m00_rs
-
-
- axi_intercon_4x64_256_bd_m00_rs_0
- 4
- 1
- 1
- 1
-
-
-
- s00_rs
-
-
- axi_intercon_4x64_256_bd_s00_rs_0
- 1
- 1
- 1
- 1
- 1
-
-
-
- s00_width_conv
-
-
- axi_intercon_4x64_256_bd_s00_width_conv_0
- 64
- 256
- 2
- 1
- 2
-
-
-
- s01_rs
-
-
- axi_intercon_4x64_256_bd_s01_rs_0
- 1
- 1
- 1
- 1
- 1
-
-
-
- s01_width_conv
-
-
- axi_intercon_4x64_256_bd_s01_width_conv_0
- 64
- 256
- 2
- 1
- 2
-
-
-
- xbar
-
-
- axi_intercon_4x64_256_bd_xbar_0
- 4
- 1
- 2
- 256
- SAMD
- 4
- 0
- 0x00000004
- 0x00000008
- 0x0000000c
- 0x00000010
- 0x00000014
- 0x00000018
- 0x0000001c
- 0x00000020
- 0x00000024
- 0x00000028
- 0x0000002c
- 0x00000030
- 0x00000034
- 0x00000038
- 0x0000003c
-
-
-
- s01_rs_256
-
-
- axi_intercon_4x64_256_bd_s01_rs_256_0
- 1
- 1
- 1
- 1
- 1
-
-
-
- s00_rs_256
-
-
- axi_intercon_4x64_256_bd_s00_rs_256_0
- 1
- 1
- 1
- 1
- 1
-
-
-
- s02_rs
-
-
- axi_intercon_4x64_256_bd_s02_rs_0
- 1
- 1
- 1
- 1
- 1
-
-
-
- s03_rs
-
-
- axi_intercon_4x64_256_bd_s03_rs_0
- 1
- 1
- 1
- 1
- 1
-
-
-
- s02_width_conv
-
-
- axi_intercon_4x64_256_bd_s02_width_conv_0
- 64
- 256
- 2
- 1
- 2
-
-
-
- s03_width_conv
-
-
- axi_intercon_4x64_256_bd_s03_width_conv_0
- 64
- 256
- 2
- 1
- 2
-
-
-
- s03_rs_256
-
-
- axi_intercon_4x64_256_bd_s03_rs_256_0
- 1
- 1
- 1
- 1
- 1
-
-
-
- s02_rs_256
-
-
- axi_intercon_4x64_256_bd_s02_rs_256_0
- 1
- 1
- 1
- 1
- 1
-
-
-
-
-
- s00_rs_M_AXI
-
-
-
-
- s01_rs_M_AXI
-
-
-
-
- xbar_M00_AXI
-
-
-
-
- s00_rs_256_M_AXI
-
-
-
-
- s01_rs_256_M_AXI
-
-
-
-
- s00_width_conv_M_AXI
-
-
-
-
- s01_width_conv_M_AXI
-
-
-
-
- s02_rs_M_AXI
-
-
-
-
- s03_rs_M_AXI
-
-
-
-
- s02_width_conv_M_AXI
-
-
-
-
- s03_width_conv_M_AXI
-
-
-
-
- s02_rs_256_M_AXI
-
-
-
-
- s03_rs_256_M_AXI
-
-
-
-
-
-
- M00_AXI_ACLK_1
-
-
-
-
-
-
-
-
-
-
-
-
-
- M00_AXI_ARESETN_1
-
-
-
-
-
-
-
-
-
-
-
-
-
- S00_AXI_ACLK_1
-
-
-
-
-
- S00_AXI_ARESETN_1
-
-
-
-
-
- S01_AXI_ACLK_1
-
-
-
-
-
- S01_AXI_ARESETN_1
-
-
-
-
-
- S02_AXI_ACLK_1
-
-
-
-
-
- S02_AXI_ARESETN_1
-
-
-
-
-
- S03_AXI_ACLK_1
-
-
-
-
-
- S03_AXI_ARESETN_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+{
+ "design": {
+ "design_info": {
+ "boundary_crc": "0x79F5CBFFB3FAB4CA",
+ "device": "xc7z100ffg900-2",
+ "name": "axi_intercon_4x64_256_bd",
+ "synth_flow_mode": "None",
+ "tool_version": "2019.1.1_AR73068",
+ "validated": "true"
+ },
+ "design_tree": {
+ "m00_rs": "",
+ "s00_rs": "",
+ "s00_width_conv": "",
+ "s01_rs": "",
+ "s01_width_conv": "",
+ "xbar": "",
+ "s01_rs_256": "",
+ "s00_rs_256": "",
+ "s02_rs": "",
+ "s03_rs": "",
+ "s02_width_conv": "",
+ "s03_width_conv": "",
+ "s03_rs_256": "",
+ "s02_rs_256": ""
+ },
+ "interface_ports": {
+ "M00_AXI": {
+ "mode": "Master",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+ "parameters": {
+ "ADDR_WIDTH": {
+ "value": "32"
+ },
+ "ARUSER_WIDTH": {
+ "value": "0",
+ "value_src": "ip_prop"
+ },
+ "AWUSER_WIDTH": {
+ "value": "0",
+ "value_src": "ip_prop"
+ },
+ "BUSER_WIDTH": {
+ "value": "0",
+ "value_src": "ip_prop"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_M00_ACLK"
+ },
+ "DATA_WIDTH": {
+ "value": "256"
+ },
+ "FREQ_HZ": {
+ "value": "200000000"
+ },
+ "HAS_BRESP": {
+ "value": "1",
+ "value_src": "const_prop"
+ },
+ "HAS_BURST": {
+ "value": "1",
+ "value_src": "default"
+ },
+ "HAS_CACHE": {
+ "value": "1",
+ "value_src": "default"
+ },
+ "HAS_LOCK": {
+ "value": "1",
+ "value_src": "default"
+ },
+ "HAS_PROT": {
+ "value": "1",
+ "value_src": "const_prop"
+ },
+ "HAS_QOS": {
+ "value": "1",
+ "value_src": "default"
+ },
+ "HAS_REGION": {
+ "value": "1",
+ "value_src": "default"
+ },
+ "HAS_RRESP": {
+ "value": "1",
+ "value_src": "default"
+ },
+ "HAS_WSTRB": {
+ "value": "1",
+ "value_src": "const_prop"
+ },
+ "ID_WIDTH": {
+ "value": "4",
+ "value_src": "user_prop"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "MAX_BURST_LENGTH": {
+ "value": "256",
+ "value_src": "ip_prop"
+ },
+ "NUM_READ_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_READ_THREADS": {
+ "value": "1",
+ "value_src": "ip_prop"
+ },
+ "NUM_WRITE_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_WRITE_THREADS": {
+ "value": "1",
+ "value_src": "ip_prop"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ },
+ "PROTOCOL": {
+ "value": "AXI4"
+ },
+ "READ_WRITE_MODE": {
+ "value": "READ_WRITE",
+ "value_src": "ip_prop"
+ },
+ "RUSER_BITS_PER_BYTE": {
+ "value": "0",
+ "value_src": "ip_prop"
+ },
+ "RUSER_WIDTH": {
+ "value": "0",
+ "value_src": "ip_prop"
+ },
+ "SUPPORTS_NARROW_BURST": {
+ "value": "1",
+ "value_src": "ip_prop"
+ },
+ "WUSER_BITS_PER_BYTE": {
+ "value": "0",
+ "value_src": "ip_prop"
+ },
+ "WUSER_WIDTH": {
+ "value": "0",
+ "value_src": "ip_prop"
+ }
+ }
+ },
+ "S00_AXI": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+ "parameters": {
+ "ADDR_WIDTH": {
+ "value": "32"
+ },
+ "ARUSER_WIDTH": {
+ "value": "0"
+ },
+ "AWUSER_WIDTH": {
+ "value": "0"
+ },
+ "BUSER_WIDTH": {
+ "value": "0"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_S00_ACLK"
+ },
+ "DATA_WIDTH": {
+ "value": "64"
+ },
+ "FREQ_HZ": {
+ "value": "350000000",
+ "value_src": "default"
+ },
+ "HAS_BRESP": {
+ "value": "1"
+ },
+ "HAS_BURST": {
+ "value": "1"
+ },
+ "HAS_CACHE": {
+ "value": "1"
+ },
+ "HAS_LOCK": {
+ "value": "1"
+ },
+ "HAS_PROT": {
+ "value": "1"
+ },
+ "HAS_QOS": {
+ "value": "1"
+ },
+ "HAS_REGION": {
+ "value": "1"
+ },
+ "HAS_RRESP": {
+ "value": "1"
+ },
+ "HAS_WSTRB": {
+ "value": "1"
+ },
+ "ID_WIDTH": {
+ "value": "1"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "MAX_BURST_LENGTH": {
+ "value": "256"
+ },
+ "NUM_READ_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_READ_THREADS": {
+ "value": "1"
+ },
+ "NUM_WRITE_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_WRITE_THREADS": {
+ "value": "1"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ },
+ "PROTOCOL": {
+ "value": "AXI4"
+ },
+ "READ_WRITE_MODE": {
+ "value": "READ_WRITE"
+ },
+ "RUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "RUSER_WIDTH": {
+ "value": "0"
+ },
+ "SUPPORTS_NARROW_BURST": {
+ "value": "1"
+ },
+ "WUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "WUSER_WIDTH": {
+ "value": "0"
+ }
+ }
+ },
+ "S01_AXI": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+ "parameters": {
+ "ADDR_WIDTH": {
+ "value": "32"
+ },
+ "ARUSER_WIDTH": {
+ "value": "0"
+ },
+ "AWUSER_WIDTH": {
+ "value": "0"
+ },
+ "BUSER_WIDTH": {
+ "value": "0"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_S01_ACLK"
+ },
+ "DATA_WIDTH": {
+ "value": "64"
+ },
+ "FREQ_HZ": {
+ "value": "350000000",
+ "value_src": "default"
+ },
+ "HAS_BRESP": {
+ "value": "1"
+ },
+ "HAS_BURST": {
+ "value": "1"
+ },
+ "HAS_CACHE": {
+ "value": "1"
+ },
+ "HAS_LOCK": {
+ "value": "1"
+ },
+ "HAS_PROT": {
+ "value": "1"
+ },
+ "HAS_QOS": {
+ "value": "1"
+ },
+ "HAS_REGION": {
+ "value": "1"
+ },
+ "HAS_RRESP": {
+ "value": "1"
+ },
+ "HAS_WSTRB": {
+ "value": "1"
+ },
+ "ID_WIDTH": {
+ "value": "1"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "MAX_BURST_LENGTH": {
+ "value": "256"
+ },
+ "NUM_READ_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_READ_THREADS": {
+ "value": "1"
+ },
+ "NUM_WRITE_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_WRITE_THREADS": {
+ "value": "1"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ },
+ "PROTOCOL": {
+ "value": "AXI4"
+ },
+ "READ_WRITE_MODE": {
+ "value": "READ_WRITE"
+ },
+ "RUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "RUSER_WIDTH": {
+ "value": "0"
+ },
+ "SUPPORTS_NARROW_BURST": {
+ "value": "1"
+ },
+ "WUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "WUSER_WIDTH": {
+ "value": "0"
+ }
+ }
+ },
+ "S02_AXI": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+ "parameters": {
+ "ADDR_WIDTH": {
+ "value": "32"
+ },
+ "ARUSER_WIDTH": {
+ "value": "0"
+ },
+ "AWUSER_WIDTH": {
+ "value": "0"
+ },
+ "BUSER_WIDTH": {
+ "value": "0"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_S00_ACLK"
+ },
+ "DATA_WIDTH": {
+ "value": "64"
+ },
+ "FREQ_HZ": {
+ "value": "350000000",
+ "value_src": "default"
+ },
+ "HAS_BRESP": {
+ "value": "1"
+ },
+ "HAS_BURST": {
+ "value": "1"
+ },
+ "HAS_CACHE": {
+ "value": "1"
+ },
+ "HAS_LOCK": {
+ "value": "1"
+ },
+ "HAS_PROT": {
+ "value": "1"
+ },
+ "HAS_QOS": {
+ "value": "1"
+ },
+ "HAS_REGION": {
+ "value": "1"
+ },
+ "HAS_RRESP": {
+ "value": "1"
+ },
+ "HAS_WSTRB": {
+ "value": "1"
+ },
+ "ID_WIDTH": {
+ "value": "1"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "MAX_BURST_LENGTH": {
+ "value": "256"
+ },
+ "NUM_READ_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_READ_THREADS": {
+ "value": "1"
+ },
+ "NUM_WRITE_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_WRITE_THREADS": {
+ "value": "1"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ },
+ "PROTOCOL": {
+ "value": "AXI4"
+ },
+ "READ_WRITE_MODE": {
+ "value": "READ_WRITE"
+ },
+ "RUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "RUSER_WIDTH": {
+ "value": "0"
+ },
+ "SUPPORTS_NARROW_BURST": {
+ "value": "1"
+ },
+ "WUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "WUSER_WIDTH": {
+ "value": "0"
+ }
+ }
+ },
+ "S03_AXI": {
+ "mode": "Slave",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+ "parameters": {
+ "ADDR_WIDTH": {
+ "value": "32"
+ },
+ "ARUSER_WIDTH": {
+ "value": "0"
+ },
+ "AWUSER_WIDTH": {
+ "value": "0"
+ },
+ "BUSER_WIDTH": {
+ "value": "0"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_S00_ACLK"
+ },
+ "DATA_WIDTH": {
+ "value": "64"
+ },
+ "FREQ_HZ": {
+ "value": "350000000",
+ "value_src": "default"
+ },
+ "HAS_BRESP": {
+ "value": "1"
+ },
+ "HAS_BURST": {
+ "value": "1"
+ },
+ "HAS_CACHE": {
+ "value": "1"
+ },
+ "HAS_LOCK": {
+ "value": "1"
+ },
+ "HAS_PROT": {
+ "value": "1"
+ },
+ "HAS_QOS": {
+ "value": "1"
+ },
+ "HAS_REGION": {
+ "value": "1"
+ },
+ "HAS_RRESP": {
+ "value": "1"
+ },
+ "HAS_WSTRB": {
+ "value": "1"
+ },
+ "ID_WIDTH": {
+ "value": "1"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "MAX_BURST_LENGTH": {
+ "value": "256"
+ },
+ "NUM_READ_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_READ_THREADS": {
+ "value": "1"
+ },
+ "NUM_WRITE_OUTSTANDING": {
+ "value": "2"
+ },
+ "NUM_WRITE_THREADS": {
+ "value": "1"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ },
+ "PROTOCOL": {
+ "value": "AXI4"
+ },
+ "READ_WRITE_MODE": {
+ "value": "READ_WRITE"
+ },
+ "RUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "RUSER_WIDTH": {
+ "value": "0"
+ },
+ "SUPPORTS_NARROW_BURST": {
+ "value": "1"
+ },
+ "WUSER_BITS_PER_BYTE": {
+ "value": "0"
+ },
+ "WUSER_WIDTH": {
+ "value": "0"
+ }
+ }
+ }
+ },
+ "ports": {
+ "M00_AXI_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "M00_AXI",
+ "value_src": "default"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "M00_AXI_ARESETN"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_M00_ACLK"
+ },
+ "FREQ_HZ": {
+ "value": "200000000"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ }
+ }
+ },
+ "M00_AXI_ARESETN": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "default"
+ }
+ }
+ },
+ "S00_AXI_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "S00_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "S00_AXI_ARESETN"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_S00_ACLK"
+ },
+ "FREQ_HZ": {
+ "value": "350000000"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ }
+ }
+ },
+ "S00_AXI_ARESETN": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "default"
+ }
+ }
+ },
+ "S01_AXI_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "S01_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "S01_AXI_ARESETN"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_S01_ACLK"
+ },
+ "FREQ_HZ": {
+ "value": "350000000"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ }
+ }
+ },
+ "S01_AXI_ARESETN": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "default"
+ }
+ }
+ },
+ "S02_AXI_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "S02_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "S00_AXI_ARESETN:S02_AXI_ARESETN"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_S00_ACLK"
+ },
+ "FREQ_HZ": {
+ "value": "350000000"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ }
+ }
+ },
+ "S02_AXI_ARESETN": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "default"
+ }
+ }
+ },
+ "S03_AXI_ACLK": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "S02_AXI:S03_AXI"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "S00_AXI_ARESETN:S02_AXI_ARESETN:S03_AXI_ARESETN"
+ },
+ "CLK_DOMAIN": {
+ "value": "axi_intercon_4x64_128_bd_S00_ACLK"
+ },
+ "FREQ_HZ": {
+ "value": "350000000"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.000",
+ "value_src": "default"
+ }
+ }
+ },
+ "S03_AXI_ARESETN": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "default"
+ }
+ }
+ }
+ },
+ "components": {
+ "m00_rs": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_m00_rs_0",
+ "parameters": {
+ "ID_WIDTH": {
+ "value": "4"
+ },
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ }
+ }
+ },
+ "s00_rs": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s00_rs_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
+ }
+ }
+ },
+ "s00_width_conv": {
+ "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s00_width_conv_0",
+ "parameters": {
+ "ACLK_ASYNC": {
+ "value": "1"
+ },
+ "FIFO_MODE": {
+ "value": "2"
+ },
+ "MI_DATA_WIDTH": {
+ "value": "256"
+ },
+ "SI_DATA_WIDTH": {
+ "value": "64"
+ },
+ "SYNCHRONIZATION_STAGES": {
+ "value": "2"
+ }
+ }
+ },
+ "s01_rs": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s01_rs_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
+ }
+ }
+ },
+ "s01_width_conv": {
+ "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s01_width_conv_0",
+ "parameters": {
+ "ACLK_ASYNC": {
+ "value": "1"
+ },
+ "FIFO_MODE": {
+ "value": "2"
+ },
+ "MI_DATA_WIDTH": {
+ "value": "256"
+ },
+ "SI_DATA_WIDTH": {
+ "value": "64"
+ },
+ "SYNCHRONIZATION_STAGES": {
+ "value": "2"
+ }
+ }
+ },
+ "xbar": {
+ "vlnv": "xilinx.com:ip:axi_crossbar:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_xbar_0",
+ "parameters": {
+ "CONNECTIVITY_MODE": {
+ "value": "SAMD"
+ },
+ "DATA_WIDTH": {
+ "value": "256"
+ },
+ "ID_WIDTH": {
+ "value": "4"
+ },
+ "NUM_MI": {
+ "value": "1"
+ },
+ "NUM_SI": {
+ "value": "4"
+ },
+ "S00_SINGLE_THREAD": {
+ "value": "0"
+ },
+ "S01_BASE_ID": {
+ "value": "0x00000004"
+ },
+ "S02_BASE_ID": {
+ "value": "0x00000008"
+ },
+ "S03_BASE_ID": {
+ "value": "0x0000000c"
+ },
+ "S04_BASE_ID": {
+ "value": "0x00000010"
+ },
+ "S05_BASE_ID": {
+ "value": "0x00000014"
+ },
+ "S06_BASE_ID": {
+ "value": "0x00000018"
+ },
+ "S07_BASE_ID": {
+ "value": "0x0000001c"
+ },
+ "S08_BASE_ID": {
+ "value": "0x00000020"
+ },
+ "S09_BASE_ID": {
+ "value": "0x00000024"
+ },
+ "S10_BASE_ID": {
+ "value": "0x00000028"
+ },
+ "S11_BASE_ID": {
+ "value": "0x0000002c"
+ },
+ "S12_BASE_ID": {
+ "value": "0x00000030"
+ },
+ "S13_BASE_ID": {
+ "value": "0x00000034"
+ },
+ "S14_BASE_ID": {
+ "value": "0x00000038"
+ },
+ "S15_BASE_ID": {
+ "value": "0x0000003c"
+ },
+ "STRATEGY": {
+ "value": "2"
+ }
+ }
+ },
+ "s01_rs_256": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s01_rs_256_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
+ }
+ }
+ },
+ "s00_rs_256": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s00_rs_256_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
+ }
+ }
+ },
+ "s02_rs": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s02_rs_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
+ }
+ }
+ },
+ "s03_rs": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s03_rs_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
+ }
+ }
+ },
+ "s02_width_conv": {
+ "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s02_width_conv_0",
+ "parameters": {
+ "ACLK_ASYNC": {
+ "value": "1"
+ },
+ "FIFO_MODE": {
+ "value": "2"
+ },
+ "MI_DATA_WIDTH": {
+ "value": "256"
+ },
+ "SI_DATA_WIDTH": {
+ "value": "64"
+ },
+ "SYNCHRONIZATION_STAGES": {
+ "value": "2"
+ }
+ }
+ },
+ "s03_width_conv": {
+ "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s03_width_conv_0",
+ "parameters": {
+ "ACLK_ASYNC": {
+ "value": "1"
+ },
+ "FIFO_MODE": {
+ "value": "2"
+ },
+ "MI_DATA_WIDTH": {
+ "value": "256"
+ },
+ "SI_DATA_WIDTH": {
+ "value": "64"
+ },
+ "SYNCHRONIZATION_STAGES": {
+ "value": "2"
+ }
+ }
+ },
+ "s03_rs_256": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s03_rs_256_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
+ }
+ }
+ },
+ "s02_rs_256": {
+ "vlnv": "xilinx.com:ip:axi_register_slice:2.1",
+ "xci_name": "axi_intercon_4x64_256_bd_s02_rs_256_0",
+ "parameters": {
+ "REG_AR": {
+ "value": "1"
+ },
+ "REG_AW": {
+ "value": "1"
+ },
+ "REG_B": {
+ "value": "1"
+ },
+ "REG_R": {
+ "value": "1"
+ },
+ "REG_W": {
+ "value": "1"
+ }
+ }
+ }
+ },
+ "interface_nets": {
+ "S00_AXI_1": {
+ "interface_ports": [
+ "S00_AXI",
+ "s00_rs/S_AXI"
+ ]
+ },
+ "s03_width_conv_M_AXI": {
+ "interface_ports": [
+ "s03_width_conv/M_AXI",
+ "s03_rs_256/S_AXI"
+ ]
+ },
+ "s01_rs_256_M_AXI": {
+ "interface_ports": [
+ "s01_rs_256/M_AXI",
+ "xbar/S01_AXI"
+ ]
+ },
+ "s00_rs_256_M_AXI": {
+ "interface_ports": [
+ "s00_rs_256/M_AXI",
+ "xbar/S00_AXI"
+ ]
+ },
+ "s01_rs_M_AXI": {
+ "interface_ports": [
+ "s01_rs/M_AXI",
+ "s01_width_conv/S_AXI"
+ ]
+ },
+ "xbar_M00_AXI": {
+ "interface_ports": [
+ "m00_rs/S_AXI",
+ "xbar/M00_AXI"
+ ]
+ },
+ "s00_width_conv_M_AXI": {
+ "interface_ports": [
+ "s00_width_conv/M_AXI",
+ "s00_rs_256/S_AXI"
+ ]
+ },
+ "s03_rs_256_M_AXI": {
+ "interface_ports": [
+ "s03_rs_256/M_AXI",
+ "xbar/S03_AXI"
+ ]
+ },
+ "s02_rs_M_AXI": {
+ "interface_ports": [
+ "s02_rs/M_AXI",
+ "s02_width_conv/S_AXI"
+ ]
+ },
+ "s03_rs_M_AXI": {
+ "interface_ports": [
+ "s03_rs/M_AXI",
+ "s03_width_conv/S_AXI"
+ ]
+ },
+ "s00_rs_M_AXI": {
+ "interface_ports": [
+ "s00_rs/M_AXI",
+ "s00_width_conv/S_AXI"
+ ]
+ },
+ "s02_rs_256_M_AXI": {
+ "interface_ports": [
+ "s02_rs_256/M_AXI",
+ "xbar/S02_AXI"
+ ]
+ },
+ "s01_width_conv_M_AXI": {
+ "interface_ports": [
+ "s01_width_conv/M_AXI",
+ "s01_rs_256/S_AXI"
+ ]
+ },
+ "s02_width_conv_M_AXI": {
+ "interface_ports": [
+ "s02_width_conv/M_AXI",
+ "s02_rs_256/S_AXI"
+ ]
+ },
+ "S03_AXI_1": {
+ "interface_ports": [
+ "S03_AXI",
+ "s03_rs/S_AXI"
+ ]
+ },
+ "m00_rs_M_AXI": {
+ "interface_ports": [
+ "M00_AXI",
+ "m00_rs/M_AXI"
+ ]
+ },
+ "S02_AXI_1": {
+ "interface_ports": [
+ "S02_AXI",
+ "s02_rs/S_AXI"
+ ]
+ },
+ "S01_AXI_1": {
+ "interface_ports": [
+ "S01_AXI",
+ "s01_rs/S_AXI"
+ ]
+ }
+ },
+ "nets": {
+ "M00_AXI_ACLK_1": {
+ "ports": [
+ "M00_AXI_ACLK",
+ "xbar/aclk",
+ "m00_rs/aclk",
+ "s00_rs_256/aclk",
+ "s01_rs_256/aclk",
+ "s01_width_conv/m_axi_aclk",
+ "s00_width_conv/m_axi_aclk",
+ "s02_width_conv/m_axi_aclk",
+ "s03_width_conv/m_axi_aclk",
+ "s02_rs_256/aclk",
+ "s03_rs_256/aclk"
+ ]
+ },
+ "M00_AXI_ARESETN_1": {
+ "ports": [
+ "M00_AXI_ARESETN",
+ "xbar/aresetn",
+ "m00_rs/aresetn",
+ "s00_rs_256/aresetn",
+ "s01_rs_256/aresetn",
+ "s01_width_conv/m_axi_aresetn",
+ "s00_width_conv/m_axi_aresetn",
+ "s02_width_conv/m_axi_aresetn",
+ "s03_width_conv/m_axi_aresetn",
+ "s02_rs_256/aresetn",
+ "s03_rs_256/aresetn"
+ ]
+ },
+ "S00_AXI_ACLK_1": {
+ "ports": [
+ "S00_AXI_ACLK",
+ "s00_rs/aclk",
+ "s00_width_conv/s_axi_aclk"
+ ]
+ },
+ "S00_AXI_ARESETN_1": {
+ "ports": [
+ "S00_AXI_ARESETN",
+ "s00_rs/aresetn",
+ "s00_width_conv/s_axi_aresetn"
+ ]
+ },
+ "S01_AXI_ACLK_1": {
+ "ports": [
+ "S01_AXI_ACLK",
+ "s01_rs/aclk",
+ "s01_width_conv/s_axi_aclk"
+ ]
+ },
+ "S01_AXI_ARESETN_1": {
+ "ports": [
+ "S01_AXI_ARESETN",
+ "s01_rs/aresetn",
+ "s01_width_conv/s_axi_aresetn"
+ ]
+ },
+ "S02_AXI_ACLK_1": {
+ "ports": [
+ "S02_AXI_ACLK",
+ "s02_rs/aclk",
+ "s02_width_conv/s_axi_aclk"
+ ]
+ },
+ "S02_AXI_ARESETN_1": {
+ "ports": [
+ "S02_AXI_ARESETN",
+ "s02_rs/aresetn",
+ "s02_width_conv/s_axi_aresetn"
+ ]
+ },
+ "S03_AXI_ACLK_1": {
+ "ports": [
+ "S03_AXI_ACLK",
+ "s03_rs/aclk",
+ "s03_width_conv/s_axi_aclk"
+ ]
+ },
+ "S03_AXI_ARESETN_1": {
+ "ports": [
+ "S03_AXI_ARESETN",
+ "s03_rs/aresetn",
+ "s03_width_conv/s_axi_aresetn"
+ ]
+ }
+ },
+ "addressing": {
+ "/": {
+ "address_spaces": {
+ "S00_AXI": {
+ "range": "4G",
+ "width": "32",
+ "segments": {
+ "SEG_M00_AXI_Reg": {
+ "address_block": "/M00_AXI/Reg",
+ "offset": "0x00000000",
+ "range": "2G"
+ }
+ }
+ },
+ "S01_AXI": {
+ "range": "4G",
+ "width": "32",
+ "segments": {
+ "SEG_M00_AXI_Reg": {
+ "address_block": "/M00_AXI/Reg",
+ "offset": "0x00000000",
+ "range": "2G"
+ }
+ }
+ },
+ "S02_AXI": {
+ "range": "4G",
+ "width": "32",
+ "segments": {
+ "SEG_M00_AXI_Reg": {
+ "address_block": "/M00_AXI/Reg",
+ "offset": "0x00000000",
+ "range": "2G"
+ }
+ }
+ },
+ "S03_AXI": {
+ "range": "4G",
+ "width": "32",
+ "segments": {
+ "SEG_M00_AXI_Reg": {
+ "address_block": "/M00_AXI/Reg",
+ "offset": "0x00000000",
+ "range": "2G"
+ }
+ }
+ }
+ },
+ "memory_maps": {
+ "M00_AXI": {
+ "address_blocks": {
+ "Reg": {
+ "base_address": "0",
+ "range": "64K",
+ "width": "32",
+ "usage": "register"
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml b/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml
index 2175977..a5bded5 100644
--- a/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml
+++ b/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml
@@ -1,10 +1,11 @@
-
+
Composite Fileset
-
-
-
+
+
+
+