miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
64 Commits 1 Branch 0 Tags
a46e351a6522a242d754d6e1c725916909363dd2
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Wade Fife a46e351a65 fpga: rfnoc: Add RFNoC Add/Sub block 
Original-commit: 5134b6caea58da825c4da1888a4d26888acc126a
2020-05-28 15:04:05 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: rfnoc: Add RFNoC Add/Sub block
2020-05-28 15:04:05 -05:00
sim
fpga: sim: Add packet_info_equal function
2020-05-28 15:04:05 -05:00
tools
fpga: tools: Improve native ModelSim support
2020-05-26 13:36:55 -05:00
top
x300: Expand DRAM address space to 1G
2020-05-18 17:50:38 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
S
Description
No description provided
84 MiB
Languages
Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%