Wade Fife d3615aefe0 fpga: tools: Improve native ModelSim support ...

This adds support for colored output and support for directories added
to the list of source files (for HLS support).


Original-commit: 5b3d66e5b7cedb7098de3e4dbbee70af04a3626e

2020-05-26 13:36:55 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Add Vector IIR RFNoC block

2020-05-19 14:22:55 -05:00

sim

fpga: sim: Don't affect packet arguments in chdr_to_axis

2020-05-04 23:40:25 -05:00

tools

fpga: tools: Improve native ModelSim support

2020-05-26 13:36:55 -05:00

top

x300: Expand DRAM address space to 1G

2020-05-18 17:50:38 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%