Wade Fife cb04b641a3 x300: Expand DRAM address space to 1G ...

The address ranges configured for the AXI interconnect IP limited the
amount of accessible DRAM to two 32 MB regions. This change makes the
full 1G available to all DRAM ports.


Original-commit: bba0cddfadcb744e8a6fae27d57ba8d3995eaf64

2020-05-18 17:50:38 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Clean up ctrlport_splitter usage

2020-05-12 13:46:28 -05:00

sim

fpga: sim: Don't affect packet arguments in chdr_to_axis

2020-05-04 23:40:25 -05:00

tools

fpga: tools: Fix HLS IP build with Cygwin

2020-05-12 13:47:20 -05:00

top

x300: Expand DRAM address space to 1G

2020-05-18 17:50:38 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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