miegl/b210-k7-fpga
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Wade Fife 2711d7f618 sim: Add ChdrIfaceBfm test 
Original-commit: 6f42ab7c1c962bfc425b6790fe41b2c14769e561
2020-03-09 13:43:05 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
sim: Add item support to RFNoC simulation
2020-03-09 13:43:05 -05:00
sim
sim: Add ChdrIfaceBfm test
2020-03-09 13:43:05 -05:00
tools
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
top
rfnoc: Add management filter to generic xport
2020-02-19 13:27:16 -06:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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84 MiB
Languages
Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%