Wade Fife 8ed69c7cdb fpga: rfnoc: Fix clock crossing in axis_data_to_chdr ...

This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.

Also cleans up trailing white space.


Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1

2020-08-12 13:56:13 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Fix clock crossing in axis_data_to_chdr

2020-08-12 13:56:13 -05:00

sim

fpga: sim: Update PkgEthernet

2020-07-31 13:22:29 -05:00

tools

fpga: tools: RESOLVE_PATH checks for an empty path

2020-07-30 15:00:06 -05:00

top

fpga: n320: Add BIST (AA) image files

2020-07-31 14:32:54 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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