Wade Fife dce6ce8063 fpga: rfnoc: Fix testbenches to run under ModelSim ...

This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.


Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b

2020-07-20 15:33:22 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Fix testbenches to run under ModelSim

2020-07-20 15:33:22 -05:00

sim

fpga: lib: Add synthesizable AXI4-Stream SV components

2020-06-25 14:44:04 -05:00

tools

fpga: lib: Add width agnostic version of Ethernet Interface

2020-06-30 10:29:35 -05:00

top

fpga: rfnoc: Fix testbenches to run under ModelSim

2020-07-20 15:33:22 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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