fpga: rfnoc: Fix testbenches to run under ModelSim
This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work. Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
This commit is contained in:
Wade Fife
@@ -1,5 +1,5 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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# Copyright 2019 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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@@ -7,57 +7,43 @@
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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# Define BASE_DIR to point to the "top" dir. Note:
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# UHD_FPGA_DIR must be passed into this Makefile.
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BASE_DIR = ../../../../top
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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LIB_IP_DIR = $(BASE_DIR)/../lib/ip
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# Include makefiles and sources for all IP components
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# *after* defining the LIB_IP_DIR
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#include $(LIB_IP_DIR)/axi_fft/Makefile.inc
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#include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc
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include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
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include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
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include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
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$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \
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$(COREGEN_DSP_SRCS) \
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)
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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# Include makefiles and sources for the DUT and its
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# dependencies.
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
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include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
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include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs
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include Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
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$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \
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$(COREGEN_DSP_SRCS) \
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$(RFNOC_BLOCK_DDC_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = rfnoc_block_ddc_tb
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# Add test bench, user design under test, and
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# additional user created files
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MODELSIM_LIBS += unimacro_ver
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SIM_TOP = rfnoc_block_ddc_tb glbl
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SIM_SRCS = \
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$(COREGEN_DSP_SRCS) \
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$(abspath rfnoc_block_ddc_tb.sv)
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$(abspath $(IP_BUILD_DIR)/dds_sin_cos_lut_only/sim/dds_sin_cos_lut_only.vhd) \
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$(abspath $(IP_BUILD_DIR)/complex_multiplier_dds/sim/complex_multiplier_dds.vhd) \
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$(abspath rfnoc_block_ddc_tb.sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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#-------------------------------------------------
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# Bottom-of-Makefile
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@@ -1,5 +1,5 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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# Copyright 2019 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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@@ -1,5 +1,5 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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# Copyright 2019 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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@@ -7,56 +7,51 @@
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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# Define BASE_DIR to point to the "top" dir. Note:
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# UHD_FPGA_DIR must be passed into this Makefile.
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BASE_DIR = ../../../../top
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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LIB_IP_DIR = $(BASE_DIR)/../lib/ip
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# Include makefiles and sources for all IP components
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# *after* defining the LIB_IP_DIR
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include $(LIB_IP_DIR)/axi_hb47/Makefile.inc
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include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
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include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
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include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(LIB_IP_AXI_HB47_SRCS) \
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$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
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$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \
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$(COREGEN_DSP_SRCS) \
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)
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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# Include makefiles and sources for the DUT and its
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# dependencies.
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include $(LIB_IP_DIR)/axi_hb47/Makefile.inc
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include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
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include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
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include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs
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include Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(LIB_IP_AXI_HB47_SRCS) \
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$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
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$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \
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$(COREGEN_DSP_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = rfnoc_block_duc_tb
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# Add test bench, user design under test, and
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# additional user created files
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SIM_TOP = rfnoc_block_duc_tb glbl
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SIM_SRCS = \
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$(abspath rfnoc_block_duc_tb.sv)
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$(abspath $(IP_BUILD_DIR)/dds_sin_cos_lut_only/sim/dds_sin_cos_lut_only.vhd) \
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$(abspath $(IP_BUILD_DIR)/complex_multiplier_dds/sim/complex_multiplier_dds.vhd) \
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$(abspath $(IP_BUILD_DIR)/axi_hb47/sim/axi_hb47.vhd) \
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$(abspath modelsim_proj/axi_hb47.mif) \
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$(abspath rfnoc_block_duc_tb.sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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# Copy the .mif file so ModelSim can find it
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$(abspath modelsim_proj/axi_hb47.mif) : $(LIB_IP_AXI_HB47_OUTS)
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mkdir -p modelsim_proj
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cp $(abspath $(IP_BUILD_DIR)/axi_hb47/axi_hb47.mif) $(abspath modelsim_proj/axi_hb47.mif)
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#-------------------------------------------------
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# Bottom-of-Makefile
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@@ -1,5 +1,5 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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# Copyright 2019 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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@@ -1,5 +1,5 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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# Copyright 2019 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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@@ -45,13 +45,10 @@ $(RFNOC_OOT_SRCS) \
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = rfnoc_block_fft_tb
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# Add test bench, user design under test, and
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# additional user created files
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SIM_TOP = rfnoc_block_fft_tb glbl
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SIM_SRCS = \
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$(abspath rfnoc_block_fft_tb.sv)
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$(abspath rfnoc_block_fft_tb.sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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#-------------------------------------------------
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# Bottom-of-Makefile
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@@ -1,5 +1,5 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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# Copyright 2019 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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@@ -30,13 +30,8 @@ include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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BUILD_IP_DIR = $(abspath $(BASE_DIR)/x300/build-ip/xc7k410tffg900-2)
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IP_SRC = \
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$(abspath $(BUILD_IP_DIR)/fifo_short_2clk/fifo_short_2clk_sim_netlist.v)
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# Xilinx IP wants lots of libraries
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
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MODELSIM_ARGS += glbl -t 1fs
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IP_DIR = $(BASE_DIR)/x300/ip
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include $(BASE_DIR)/x300/ip/fifo_short_2clk/Makefile.inc
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DESIGN_SRCS = $(abspath \
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eth_ifc_synth_test.sv \
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@@ -51,22 +46,26 @@ $(RFNOC_XPORT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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$(RFNOC_CORE_SRCS) \
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$(IP_SRC) \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4
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MODELSIM_ARGS += glbl -t 1fs
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# Define toplevel module
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TB_TOP_MODULE ?= eth_ifc_all_tb
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#TB_TOP_MODULE ?= eth_ifc_synth_test
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SIM_TOP = $(TB_TOP_MODULE)
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SIM_SRCS = \
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$(abspath $(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v) \
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$(abspath eth_ifc_tb.sv) \
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$(abspath $(TB_TOP_MODULE).sv)
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$(abspath $(TB_TOP_MODULE).sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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# supressing the following worthless reminder.
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# Suppressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS = -suppress 2583 -keep_delta
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@@ -25,13 +25,14 @@ $(DSP_SRCS) \
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = mult_add_clip_tb
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# Define toplevel module
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SIM_TOP = mult_add_clip_tb glbl
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# Add test bench, user design under test, and
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# additional user created files
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SIM_SRCS = $(abspath \
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mult_add_clip_tb.sv \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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)
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# MODELSIM_USER_DO = $(abspath wave.do)
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@@ -25,11 +25,12 @@ DESIGN_SRCS = $(abspath ../../e310_io.v) \
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = e310_io_tb
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# Define toplevel module
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SIM_TOP = e310_io_tb glbl
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SIM_SRCS = \
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$(abspath e310_io_tb.sv)
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$(abspath e310_io_tb.sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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#-------------------------------------------------
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# Bottom-of-Makefile
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