Wade Fife b566c415a1 fpga: lib: Add AXI-Stream splitter (axis_split) ...

The axis_split module takes a single AXI-Stream input and duplicates it
onto multiple AXI-Stream outputs. This block correctly handles the
somewhat tricky flow-control logic so that the AXI-Stream handshake
protocol is honored at all top-level ports.


Original-commit: fa0f4b2833119d57d331f592028ff9f032895c89

2020-04-14 16:37:43 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add AXI-Stream splitter (axis_split)

2020-04-14 16:37:43 -05:00

sim

fpga: sim: Export ChdrPacket in PkgRfnoBlockCtrlBfm

2020-04-14 16:37:43 -05:00

tools

fpga: tools: Option to check for full Vivado version

2020-04-14 10:43:51 -05:00

top

fpga: e31x: Update constraints to avoid timing issues

2020-04-08 17:24:15 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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