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b210-k7

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• 24c9cdb20a b210: remove obsolete set_false_path statements b210-k7 miegl 2026-08-26 22:47:43 +02:00
• a95cce3d20 rtl: remove inferred CHDR conversion latches miegl 2026-08-25 22:36:27 +02:00
• 286cde0a8d timing: bound asynchronous GPIF-radio crossings miegl 2026-08-25 22:33:46 +02:00
• e7b1ac41e0 timing: model SISO and MIMO BUFGMUX clocks miegl 2026-08-25 22:31:36 +02:00
• eb84b6c949 fifo: synchronize read-domain reset handling miegl 2026-08-25 22:22:39 +02:00
• 90e0b1d038 fifo: replace synthesized simulation FIFO miegl 2026-08-25 22:21:16 +02:00
• a83f31ec3b vivado: migrate Kintex-7 build to Vivado 2026.1 miegl 2026-08-24 17:53:26 +02:00
• 56604b2187 vivado: add reproducible 2024.1 project build miegl 2026-08-24 17:50:44 +02:00
• 3dc3446559 b200: import original Kintex-7 clone port miegl 2026-08-23 11:42:22 +02:00
• 2f5b331f30 fpga: sim: Make members accessible in RfnocBlockCtrlBfm Wade Fife 2025-04-07 16:00:57 -05:00
• dbb52a6909 fpga: x410: Fix NCO reset mechanism Friedrich Wenisch 2025-04-16 17:16:19 +02:00
• 6386d90b35 fpga: lib: Add initial value to ram_2port Markus Schill 2025-04-08 18:10:54 +02:00
• c9d2c066f3 fpga: lib: Fix pass-through mode in axi_fifo Wade Fife 2025-04-07 13:55:08 -05:00
• 009b7801f4 fpga: sim: Restore PkgChdrUtils for compatability Wade Fife 2025-04-07 08:30:03 -05:00
• dc4f2dd6e2 fpga: lib: Update FFT IP for parallel builds Wade Fife 2025-04-02 15:30:40 -05:00
• bd85dd37ff fpga: tools: Add assert option to synthesis Sam Lane 2025-03-26 21:07:43 +00:00
• f9d9b106df fpga: tools: Fix escape sequence warnings Wade Fife 2025-04-02 16:04:46 -05:00
• d742b4018f fpga: x4xx: add reset option for gearboxes Max Köhler 2025-03-26 09:18:18 +01:00
• 14e864bdb1 fpga: x440: bring back TX control remap in RFDC BD Max Köhler 2025-03-24 12:33:20 +01:00
• 88d7598bfc fpga: x400: zbx: update projects for new ctrlport modules Max Köhler 2025-03-21 09:06:25 -05:00
• 01d6ebd45e fpga: x400: cpld: update projects for new ctrlport modules Max Köhler 2025-03-21 09:03:20 -05:00
• 8dc5d3aeec fpga: lib: redirect old ctrlport modules to interface based ones Max Köhler 2025-03-19 10:20:46 +01:00
• e67d78533c fpga: bump compat number to 10.0 Max Köhler 2025-03-13 09:52:16 +01:00
• 50f20ef4ab fpga: x4xx: replace ADC/DAC info by RFDC memory Max Köhler 2025-03-11 15:58:50 +01:00
• 37b8b0d017 fpga: rfnoc: Move synthesizable code from sim to lib Wade Fife 2025-02-20 14:10:40 -06:00
• b4943f4a61 fpga: tools: Disable common simulation warnings Wade Fife 2025-03-17 09:31:40 -05:00
• 6bcbd09a6b fpga: tools: Change -onfinish to final Wade Fife 2025-03-03 11:10:06 -06:00
• 37fb9138cd fpga: tools: Add support for Questa Wade Fife 2024-11-19 14:29:15 -06:00
• c499cad53d fpga: tools: Fix issues in run_testbenches.py Wade Fife 2025-03-07 16:23:26 -06:00
• 6b19ec030c fpga: rfnoc: fft: Support multiple samples per cycle Wade Fife 2024-11-08 16:15:17 -06:00
• d7e5823047 fpga: rfnoc: fft: Add FFT packetize modules Wade Fife 2024-12-07 16:25:16 -06:00
• ef9b86ec03 fpga: tools: Fix CSV reporting in run_testbenches.py Wade Fife 2025-03-05 21:23:11 -06:00
• 7566014c96 fpga: tools: Reformat run_testbenches.py Wade Fife 2025-03-05 14:58:31 -06:00
• 307ba63f99 fpga: lib: Fix trailing bytes in eth_ipv4_chdr_adapter Wade Fife 2025-02-27 09:17:07 -06:00
• 4eb1279423 fpga: lib: Enable TUSER in eth_ipv4_interface_wrapper Wade Fife 2025-02-27 09:37:10 -06:00
• 6fe021fdcd fpga: x400: Change NUM_DRAM_BANKS to 2 on X410 X4_400 image Wade Fife 2025-02-26 08:55:37 -06:00
• cfa8afcf37 fpga: rfnoc: Fix DDC overflow issue Niels Garibaldi 2025-02-20 17:26:53 +01:00
• 2535aa4f1b fpga: sim: Add coerce function to PkgMath Niels Garibaldi 2025-02-20 17:26:53 +01:00
• 1a3bdccd51 Revert "Get rid of unnecessary bash wrappers in subprocesses.Popen" Martin Braun 2025-02-20 09:23:37 +01:00
• bb2bfbfe95 fpga: lib: Add AXI-Stream load split and merge modules Wade Fife 2024-10-02 17:23:44 -05:00
• 72432c9278 fpga: lib: Add zero-length option to axi_fifo Wade Fife 2025-02-12 10:59:10 -06:00
• 465be512e7 fpga: Ensure RX radio command FIFO does not overflow 3 people 2025-02-10 16:04:50 +01:00
• f961936a43 rfnoc: lib: introduce ctrl-port interface and BFM Max Köhler 2025-02-10 23:35:54 +01:00
• c48f8bd5f1 fpga: rfnoc: lib: add AXI FIR filter for >1 SPC Max Köhler 2025-02-10 14:24:18 +01:00
• 7446db939c fpga: x440: fix refactored rf_core_full Max Köhler 2025-02-11 08:44:49 +01:00
• 3ed06cc861 fpga: x400: refactor RFDC block diagrams and timing constraints Friedrich Wenisch 2024-10-23 08:50:01 +00:00
• f480008cf9 fpga: rfnoc: fft: Use DEFAULT on reset in axis_cp_list Wade Fife 2025-01-06 21:18:20 -06:00
• ac04bb81c4 fpga: sim: Allow DATA_WIDTH that's not a multiple of 8 Wade Fife 2024-12-09 13:46:11 -06:00
• 30180c36f0 fpga: rfnoc: Add CHDR_HEADER_W constant Wade Fife 2024-12-07 16:23:51 -06:00
• c637f538fa fpga: lib: Add TO_SIGNED to usrp_utils.svh Wade Fife 2024-12-18 13:06:47 -06:00
• a11618f3e9 fpga: sim: Add get methods for stall probability Wade Fife 2025-01-17 13:12:30 -06:00
• 39529a180d fpga: sim: Remove unused stall arguments Wade Fife 2025-01-17 13:01:03 -06:00
• c12766fd4d fpga: x400: bump FPGA compat version to 9.0 Max Köhler 2025-02-06 11:37:18 +01:00
• 4ae2f8eb5e fpga: x400: Update SYSREF Delay and capture mechanism mschill 2024-06-20 01:16:39 +02:00
• f19fa3cf82 fpga: rfnoc: Fix info FIFO overflow Wade Fife 2025-02-08 17:18:35 -06:00
• 4db1e1e86f fpga: lib: remove reset on non-control signals of ctrlport modules Max Köhler 2025-02-10 23:28:53 +01:00
• be25e4da1b fpga: rfnoc: radio: move arithmetic away from timestamp for timing Max Köhler 2024-10-22 09:28:57 +02:00
• 0f431ebdd5 fpga: lib: Update simple_spi_core documentation Markus Schill 2025-02-07 18:04:29 +01:00
• 285f7b26a1 fpga: rfnoc: radio: Improve underflow handling Wade Fife 2025-01-31 12:57:34 -06:00
• 4d5cad3310 fpga: tools: Refactor viv_ip_xci_editor.py Martin Braun 2025-02-07 10:57:48 +01:00
• 8e0831b348 fpga: Remove vivado_lab support Martin Braun 2025-01-31 14:11:37 +01:00
• b016b90dbc fpga: x400: avoid false PPS rising edge on switching sources Max Köhler 2024-09-19 05:52:56 +02:00
• 40ce83817a fpga: lib: add register stage in ipv4 chdr adapter Max Köhler 2025-01-23 00:33:28 +01:00
• 8aefaa7582 Get rid of unnecessary bash wrappers in subprocesses.Popen Frederik Pfautsch 2024-12-17 14:11:02 +01:00
• f4b6def040 fpga: x400: refactor 100GEth LBUS to AXI interface Max Köhler 2025-01-22 13:41:57 +01:00
• 067f150b75 fpga: tools: mark hash dirty with staged changes Max Köhler 2025-01-28 12:01:19 +01:00
• 8d46198250 fpga: tools: Add --build-dir to repeat_fpga_build Max Köhler 2025-01-22 15:21:14 +01:00
• 52cc1735fd fpga: lib: simplify timing in pulse stretch Max Köhler 2025-01-23 00:09:44 +01:00
• edfe117b9c fpga: rfnoc: fft: Fix tready on magnitude path Wade Fife 2025-01-17 20:08:29 -06:00
• ccdefb0c34 fpga: x400: add CMAC placement constraints Max Köhler 2025-01-03 14:08:43 +01:00
• 81f150213f fpga: rfnoc: Add new FFT block Wade Fife 2024-05-24 14:19:52 -05:00
• 0770fd4405 fpga: lib: Add axis_sideband_tuser Wade Fife 2024-05-24 14:18:01 -05:00
• 8f64fb2ee8 fpga: lib: Add axis_split_bus Wade Fife 2024-05-24 14:17:35 -05:00
• d95d0252e0 fpga: lib: Add axis_combine Wade Fife 2024-05-24 14:17:13 -05:00
• 06c18110ce fpga: lib: Add axis_data_if_packetize Wade Fife 2024-05-24 14:16:46 -05:00
• d46b94f233 fpga: lib: Add Xilinx FFT IP for various configurations Wade Fife 2024-05-24 14:14:14 -05:00
• 4f99fee248 fpga: lib: Add complex_to_magphase_int17 IP Wade Fife 2024-08-24 20:48:51 -05:00
• 7e792d4a25 fpga: rfnoc: Add SV packages for use with RFNoC Wade Fife 2024-08-14 14:49:03 -05:00
• 48d8e384b6 fpga: lib: Add usrp_utils.svh with common macros Wade Fife 2024-08-14 14:47:39 -05:00
• 82e1da1b78 fpga: lib: Cleanup axi_demux module Wade Fife 2024-08-14 16:09:11 -05:00
• 965c13e861 fpga: tools: Add JUnit XML support to run_testbenches Wade FifeandJörg Hofrichter 2024-12-09 20:03:52 -06:00
• 5a9d9a1eb2 fpga: tools: Add --ignore-warnings to repeat_fpga_build Wade Fife 2024-11-22 14:13:39 -06:00
• 5cbd981c3e fpga: x4xx: assemble x410/x440-version-info.dtsi in BUILD_DIR Joerg Hofrichter 2024-11-21 15:51:49 +01:00
• 2a89218e95 fpga: x400: add rf core ctrlport Max Köhler 2024-11-08 00:32:10 +01:00
• f07af03214 image builder: Use RADIO_NIPC parameter Martin Braun 2024-10-22 17:49:13 +02:00
• 23b44d6538 fpga: tools: Add do file for ModelSim Wade Fife 2024-10-07 19:42:55 -05:00
• 775f1330bc fpga: tools: Add parallel FPGA build support Wade Fife 2024-09-08 20:43:20 -05:00
• a460c3ca2c fpga: tools: add diamond build sanity checks Max Köhler 2024-09-24 01:36:14 +02:00
• e659f0cfdd Fix instances of sim preamble Wade Fife 2024-09-09 14:32:00 -05:00
• e01ce08634 fpga: e31x/e320/n3xx/x400: Rework device tree file generation Joerg Hofrichter 2024-09-12 13:47:25 +02:00
• 264b33a416 fpga: x400: use parameter for RFDC info in RF core full Max Köhler 2024-09-09 09:47:08 +02:00
• bea852caeb fpga: Remove build-usrp dirs when cleaning builds Wade Fife 2024-09-07 17:04:09 -05:00
• 4b93935967 fpga: x400: Make DTS output match bitstream name Wade Fife 2024-09-05 22:32:58 -05:00
• f13f084b15 fpga: Put dependencies first in Makefile SRCS list Wade Fife 2024-09-03 11:35:38 -05:00
• 71c7b9044d fpga: x400: add register in 100G Eth TX path for timing Max Köhler 2024-08-26 23:55:05 +02:00
• 82545838b2 fpga: x440: fix conditional timing constraints Max Köhler 2024-08-27 17:11:23 +02:00
• 31ecc191a3 fpga: x440: correct crossbar replay port comments Grant Meyerhoff 2024-08-23 09:15:05 -05:00
• ea4f2ff009 fpga: x440: refactor rf_core_full to use parameters on ports Max Köhler 2024-08-09 10:42:49 +02:00
• 08f8b269fa fpga: ci: remove color coding from FPGA bitfile name Max Köhler 2024-07-10 11:57:50 +00:00
• 0df7b0071c fpga: Fix warnings from building N3xx AA images Martin Braun 2024-06-27 11:04:31 +02:00