miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: tools: add diamond build sanity checks

Browse Source 
Original-commit: aa10241c7f034739da8905f862beaf0f31d286ed
This commit is contained in:
Max Köhler
2024-09-24 10:24:29 -05:00
committed by Wade Fife
parent e659f0cfdd
commit a460c3ca2c
1 changed files with 11 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tools/make/diamond_design_builder.mak
+11 -2
View File
@@ -33,9 +33,18 @@ BUILD_DIAMOND_DESIGN = \
cd $(4); \
echo "BUILDER: Implementating design..."; \
$(DIAMOND_EXE) build.tcl > $(1)_log.txt ; \
if [ $$? -ne 0 ]; \
then \
echo "BUILDER: Build failed. See $(1)_log.txt for details."; \
exit 1; \
fi; \
echo "BUILDER: Parsing reports..."; \
grep "Cumulative negative slack: 0 (0+0)" impl1/$(1)_impl1.twr ; \
if [ $$? -ne 0 ]; then exit 1; fi; \
grep "Cumulative negative slack: 0 (0+0)" impl1/$(1)_impl1.twr > /dev/null 2>&1; \
if [ $$? -ne 0 ]; \
then \
echo "BUILDER: Timing failed. See $(1)_impl1.twr for details."; \
exit 1; \
fi; \
echo "BUILDER: Generating bitfile..."; \
ddtcmd -oft -svfsingle -if $(5)/$(1)_$(5).jed \
-dev $(2) -op "FLASH Erase,Program,Verify" -revd \