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fpga: tools: Add assert option to synthesis

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Add -assert option to Vivado synthesis to allow VHDL assert statements
to be checked during synthesis.


Original-commit: 13d004fa9001823e807c4a2b72e92b20efb6f94a
This commit is contained in:
Sam Lane
2025-04-03 11:01:14 -05:00
committed by Wade Fife
parent f9d9b106df
commit bd85dd37ff
1 changed files with 2 additions and 2 deletions
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tools/scripts/viv_utils.tcl
+2 -2
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@@ -150,7 +150,7 @@ proc ::vivado_utils::synthesize_design {args} {
set incdir_args "-include_dirs $g_include_dirs"
}
set synth_cmd "synth_design -top $g_top_module -part $g_part_name"
set synth_cmd "synth_design -top $g_top_module -part $g_part_name -assert"
set synth_cmd [concat $synth_cmd $vdef_args]
set synth_cmd [concat $synth_cmd $incdir_args]
set synth_cmd [concat $synth_cmd $args]
@@ -268,7 +268,7 @@ proc ::vivado_utils::check_design {args} {
set incdir_args "-include_dirs $g_include_dirs"
}
set synth_cmd "synth_design -top $g_top_module -part $g_part_name -rtl -rtl_skip_ip -rtl_skip_constraints"
set synth_cmd "synth_design -top $g_top_module -part $g_part_name -rtl -rtl_skip_ip -rtl_skip_constraints -assert"
set synth_cmd [concat $synth_cmd $vdef_args]
set synth_cmd [concat $synth_cmd $incdir_args]
set synth_cmd [concat $synth_cmd $args]