From bd85dd37ffe02fe2623653269c9139cfdf797ad2 Mon Sep 17 00:00:00 2001 From: Sam Lane Date: Wed, 26 Mar 2025 21:07:43 +0000 Subject: [PATCH] fpga: tools: Add assert option to synthesis Add -assert option to Vivado synthesis to allow VHDL assert statements to be checked during synthesis. Original-commit: 13d004fa9001823e807c4a2b72e92b20efb6f94a --- tools/scripts/viv_utils.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/scripts/viv_utils.tcl b/tools/scripts/viv_utils.tcl index 19d74e9..d5cb324 100644 --- a/tools/scripts/viv_utils.tcl +++ b/tools/scripts/viv_utils.tcl @@ -150,7 +150,7 @@ proc ::vivado_utils::synthesize_design {args} { set incdir_args "-include_dirs $g_include_dirs" } - set synth_cmd "synth_design -top $g_top_module -part $g_part_name" + set synth_cmd "synth_design -top $g_top_module -part $g_part_name -assert" set synth_cmd [concat $synth_cmd $vdef_args] set synth_cmd [concat $synth_cmd $incdir_args] set synth_cmd [concat $synth_cmd $args] @@ -268,7 +268,7 @@ proc ::vivado_utils::check_design {args} { set incdir_args "-include_dirs $g_include_dirs" } - set synth_cmd "synth_design -top $g_top_module -part $g_part_name -rtl -rtl_skip_ip -rtl_skip_constraints" + set synth_cmd "synth_design -top $g_top_module -part $g_part_name -rtl -rtl_skip_ip -rtl_skip_constraints -assert" set synth_cmd [concat $synth_cmd $vdef_args] set synth_cmd [concat $synth_cmd $incdir_args] set synth_cmd [concat $synth_cmd $args]