Sam Lane bd85dd37ff fpga: tools: Add assert option to synthesis ...

Add -assert option to Vivado synthesis to allow VHDL assert statements
to be checked during synthesis.


Original-commit: 13d004fa9001823e807c4a2b72e92b20efb6f94a

2025-04-03 11:01:14 -05:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fpga: lib: redirect old ctrlport modules to interface based ones

2025-03-21 09:09:09 -05:00

sim

fpga: rfnoc: Move synthesizable code from sim to lib

2025-03-17 17:47:16 -05:00

tools

fpga: tools: Add assert option to synthesis

2025-04-03 11:01:14 -05:00

top

fpga: x4xx: add reset option for gearboxes

2025-04-02 08:02:11 +02:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%