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b210-k7

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• 0361a8fa3b e31x: Swap out liberio for internal Ethernet RobertWalstab 2020-06-02 16:37:56 +02:00
• 08c24691a9 e320: Swap out liberio for internal Ethernet Alex Williams 2020-01-28 16:08:20 -08:00
• c33435c1b9 fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax Max Köhler 2020-07-07 22:39:01 +02:00
• 9ce170e4d5 fpga: n3xx: Fix White Rabbit images Wade Fife 2020-06-30 15:57:23 -05:00
• 05eb1bc2f1 fpga: lib: Add width agnostic version of Ethernet Interface Andrew Moch 2020-06-25 21:49:00 +01:00
• cbe5e99e17 fpga: rfnoc: Add Log-Power block Wade Fife 2020-06-16 11:31:45 -05:00
• c3f45a92a0 fpga: rfnoc: Fix chdr_update_length function Wade Fife 2020-06-29 08:39:15 -05:00
• 9ee2157f52 fpga: rfnoc: Add RFNoC Window block Wade Fife 2020-06-08 16:22:29 -05:00
• 5f792ad48e fpga: tools: Highlight suppressible errors from vlint Wade Fife 2020-06-11 10:26:46 -05:00
• 9e0f859bb6 fpga: lib: Fix axi_packet_gate RAM dib width Wade Fife 2020-06-09 11:26:01 -05:00
• 9b0e42678f fpga: lib: Add features to axi_lite.vh Andrew Moch 2020-06-25 22:21:52 +01:00
• 23be04661f fpga: lib: Add synthesizable AXI4-Stream SV components Andrew Moch 2020-06-22 17:13:36 +01:00
• 6940db90e3 fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tb Wade Fife 2020-06-23 13:53:25 -05:00
• e008853357 fpga: lib: Add interface and model for AXI4-Lite Andrew Moch 2020-06-18 15:43:15 +01:00
• b76ad2aef5 fpga: lib: Pipeline and add clken to ip_hdr_checksum Andrew Moch 2020-06-18 16:26:59 +01:00
• 7b1174ffd9 fpga: tools: Fix ModelSim return status Wade Fife 2020-06-16 12:16:33 -05:00
• 55881469ac fpga: rfnoc: Add support for 512-bit CHDR widths Andrew Moch 2020-06-09 20:35:31 +01:00
• 8875582763 fpga: lib: add extended spi core for 64bit Max Köhler 2020-06-17 11:07:45 +02:00
• 2a8ec5df90 fpga: tools: remove temporary Xilinx directories for BD recreation Max Köhler 2020-06-15 13:14:02 +02:00
• d16d1e121c fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin Wade Fife 2020-06-11 21:28:09 -05:00
• 523414b4ae fpga: tools: Allow multiple top modules with ModelSim Wade Fife 2020-06-04 18:21:24 -05:00
• 750317582d fpga: lib: extend wb_spi ability to limit transmission length Max Köhler 2020-05-22 22:01:13 +02:00
• cb90fe98ef fpga: lib: Fix writes in axil_regport_master Andrew Moch 2020-05-08 15:28:52 +01:00
• 3cb320fae0 fpga: rfnoc: Add defaults for rate changing Wade Fife 2020-05-26 10:47:09 -05:00
• 76a1cfa60e fpga: tools: Improve detection of setupenv sourcing Wade Fife 2020-05-27 09:42:19 -05:00
• a46e351a65 fpga: rfnoc: Add RFNoC Add/Sub block Wade Fife 2020-05-14 09:07:09 -05:00
• 859accafb3 fpga: sim: Add packet_info_equal function Wade Fife 2020-05-14 09:08:21 -05:00
• 6a5a23a7a2 rfnoc: Add Split Stream RFNoC block Wade Fife 2020-04-28 15:41:35 -05:00
• d3615aefe0 fpga: tools: Improve native ModelSim support Wade Fife 2020-05-15 14:03:29 -05:00
• 98463e99d0 fpga: tools: Add contents of directories for HDL source Wade Fife 2020-05-15 14:04:38 -05:00
• af2aeccdc8 fpga: rfnoc: Add Vector IIR RFNoC block Wade Fife 2020-05-07 14:43:32 -05:00
• 17bafa621e fpga: tools: Remove uhd_image_builder Martin Braun 2020-05-14 15:48:40 -07:00
• cb04b641a3 x300: Expand DRAM address space to 1G Wade Fife 2020-05-08 15:50:52 -05:00
• 72d8f4c8d4 fpga: e31x: Replace symbolic link for Cygwin Wade Fife 2020-05-11 11:45:56 -05:00
• f5a79baba7 fpga: tools: Fix HLS IP build with Cygwin Humberto Jimenez 2020-05-11 09:10:12 -05:00
• 5188f1a6d5 fpga: rfnoc: Clean up ctrlport_splitter usage Wade Fife 2020-05-07 15:17:41 -05:00
• c2ca39a727 fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1 Wade Fife 2020-05-07 14:42:48 -05:00
• 8556184025 TwinRX: Remove decimation from frontend Michael West 2020-03-19 12:29:29 -07:00
• dc86b52fd7 DUC/DDC: Add variable time increment Michael West 2020-03-15 01:17:50 -07:00
• 45d274746f X300: Make VITA time monotonic Michael West 2020-03-15 01:04:02 -07:00
• c33b3779f9 fpga: Change default MTU to 10 Wade Fife 2020-05-08 14:18:29 -05:00
• 1de388c61b fpga: sim: Don't affect packet arguments in chdr_to_axis Wade Fife 2020-04-29 16:57:27 -05:00
• 1563d0e5af fpga: sim: Fix get_slave_data_bfm method Wade Fife 2020-04-28 19:52:42 -05:00
• 9e1d9c46d1 fpga: sim: Export return types in PkgRfnocBlockCtrlBfm Wade Fife 2020-04-28 18:08:28 -05:00
• 8220e57a17 rfnoc: Add RFNoC fosphor block Wade Fife 2020-04-14 16:23:59 -05:00
• 34d68cf4ca fpga: rfnoc: Add option to sample sideband info at start of packet Wade Fife 2020-03-31 15:05:51 -05:00
• 7e6e25df7a fpga: tools: Add -voptargs=+acc to ModelSim GUI Wade Fife 2020-03-28 16:47:32 -05:00
• c9c9543719 fpga: core: Add chdr_update_length function Wade Fife 2020-03-26 12:47:03 -05:00
• b566c415a1 fpga: lib: Add AXI-Stream splitter (axis_split) Wade Fife 2020-03-19 13:35:59 -05:00
• 2f4fe4fdbd fpga: sim: Export ChdrPacket in PkgRfnoBlockCtrlBfm Wade Fife 2020-04-02 13:03:30 -05:00
• 9e946be598 fpga: tools: Option to check for full Vivado version Humberto Jimenez 2020-04-13 14:48:48 -05:00
• 2487e7bdf8 fpga: e31x: Update constraints to avoid timing issues Wade Fife 2020-04-06 17:55:15 -05:00
• ce701301d0 fpga: tools: Add support for .sdc in Vivado Paul Butler 2020-03-30 16:59:19 -05:00
• 8bc01517ae fpga: rfnoc: Add gate to dynamically enable control-port interfaces Max Köhler 2020-03-25 11:37:53 +01:00
• 794e094218 fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1 Max Köhler 2020-03-24 11:46:38 +01:00
• dcbc6a9c78 fpga: tools: Add default Vivado install location Wade Fife 2020-03-25 11:59:25 -05:00
• 67e76118d6 fpga: tools: Add ModelSim to run_testbenches.py Wade Fife 2020-03-20 16:18:55 -05:00
• 795efc8224 fixup! fpga: tools: Add modelsim to make sim targets Wade Fife 2020-03-20 16:17:52 -05:00
• 97dcb5363d fpga: Fix errors found by linting with vsim Andrew Moch 2020-03-19 19:55:53 +01:00
• 09751b661e fpga: tools: Add modelsim to make sim targets Andrew Moch 2020-03-11 19:39:06 +01:00
• 5367ec6006 fpga: tools: Ignore BD layout info for TCL-based BD Humberto Jimenez 2020-03-11 12:21:21 -05:00
• 72f619c429 sim: Rename class typedefs Wade Fife 2020-02-26 20:45:23 -06:00
• 2711d7f618 sim: Add ChdrIfaceBfm test Wade Fife 2020-02-24 13:41:20 -06:00
• faa360a0f9 sim: Add item support to RFNoC simulation Wade Fife 2020-02-21 16:45:34 -06:00
• 14dc3950cf sim: Parameterize chdr_word_t data type Wade Fife 2020-02-21 08:35:24 -06:00
• 1db22ce4ec sim: Split PkgRfnocBlockCtrlBfm into separate packages Wade Fife 2020-02-19 08:13:36 -06:00
• 6bea1f8222 fpga: lib: Modify for loop to Verilog 2001 syntax Max Köhler 2020-03-03 14:28:30 +01:00
• ec9eb36fb9 rfnoc: Fix FIR and AXI RAM block register documentation Wade Fife 2020-02-14 09:47:45 -06:00
• 3810f5a4d9 rfnoc: Add management filter to generic xport Wade Fife 2020-02-18 12:47:54 -06:00
• 280a00b564 radio: Update TB to use new block ctrl connect Wade Fife 2020-02-18 16:01:57 -06:00
• f51c7aa780 x300: add front-panel GPIO source control eklaiandBrent Stapleton 2020-01-23 18:47:28 -08:00
• 59adae6252 rfnoc: Update blocks to use autogenerated noc_shell Wade Fife 2020-01-27 16:36:41 -06:00
• a69290143b fixup! lib: add option for output register in pps generator Humberto Jimenez 2020-01-29 16:32:15 -06:00
• cd4cfd926c lib: add option for output register in pps generator Max Köhler 2019-12-18 11:18:46 +01:00
• 6b67702ad7 Merge FPGA repository back into UHD repository +1828 people 2020-01-23 16:10:22 -08:00
• 74893643ca Removed copy of FPGA source files. Martin Braun 2014-10-07 11:25:20 +02:00
• 56e84828fe Merge branch 'maint' Martin Braun 2014-09-24 19:08:33 -07:00
• adf2da6ac7 fpga: Multiple X300 FPGA bugfixes and enhancements Ashish Chaudhari 2014-09-24 18:45:31 -07:00
• d8650bce9b fpga: Added FPGA code for B200 AD9361 host driver addition Ashish Chaudhari 2014-08-20 09:31:33 -07:00
• 6b7004c311 fpga: Added FPGA code for X300 MIMO alignment bugfix Ashish Chaudhari 2014-08-19 12:05:46 -07:00
• 85ad83d8d3 fpga: Updating FPGA code for UHD-3.7.2-rc1 Ben Hilburn 2014-07-22 15:49:02 -07:00
• 5a525c84f5 fpga: updating b200 and x300 FPGA source code for latest images Ben Hilburn 2014-05-14 11:42:19 -07:00
• 8f1cfd55b1 x300 fpga: updating FPGA code with latest bug fixes Ben Hilburn 2014-03-20 16:07:40 -07:00
• 864a1718c5 Merge branch 'maint' Nicholas Corgan 2014-03-17 07:05:11 -07:00
• bd647a7a8d Adding bootram.coe file from latest firmware changes. michael-west 2014-03-03 13:04:25 -08:00
• 65d3d1eabd fpga: removed superfluous B2x0 files Nicholas Corgan 2014-02-20 06:05:38 -08:00
• fbbc991a7d Pushing the bulk of UHD-3.7.0 code. Ben Hilburn 2014-02-14 12:05:07 -08:00
• 29086f9001 b2xx: Updating FPGA source with recent bugfixes. Ben Hilburn 2013-12-03 10:35:35 -08:00
• c91b74de33 Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus. Ben Hilburn 2013-10-10 10:17:27 -07:00