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b2xx: Updating FPGA source with recent bugfixes.

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Original-commit: 4b4365a517938b365af57674a3ab1462432c2c3a
This commit is contained in:
Ben Hilburn
2013-12-03 10:35:35 -08:00
parent c91b74de33
commit 29086f9001
103 changed files with 2001 additions and 608 deletions
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lib/control/Makefile.srcs
+1
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@@ -23,4 +23,5 @@ axi_forwarding_cam.v \
axi_test_vfifo.v \
dram_2port.v \
cvita_uart.v \
serial_to_settings.v \
))
lib/control/arb_qualify_master.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// This module forms the qualification engine for a single master as
lib/control/axi_crossbar.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`define LOG2(N) (\
N < 2 ? 0 : \
lib/control/axi_crossbar_tb.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1 ps / 1 ps
module axi_crossbar_tb;
lib/control/axi_fifo_header.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// This module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data.
lib/control/axi_forwarding_cam.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// This module implements a highly customized TCAM that enbales forwarding
lib/control/axi_slave_mux.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/control/binary_encoder.v
+42
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@@ -0,0 +1,42 @@
`define LOG2(N) (\
N < 2 ? 0 : \
N < 4 ? 1 : \
N < 8 ? 2 : \
N < 16 ? 3 : \
N < 32 ? 4 : \
N < 64 ? 5 : \
N < 128 ? 6 : \
N < 256 ? 7 : \
N < 512 ? 8 : \
N < 1024 ? 9 : \
10)
module binary_encoder
#(
parameter SIZE = 16
)
(
input [SIZE-1:0] in,
output [`LOG2(SIZE)-1:0] out
);
genvar m,n;
generate
// Loop enough times to represent the total number of input bits as an encoded value
for (m = 0; m <= `log2(SIZE-1); m = m + 1) begin: expand_or_tree
wire [SIZE-1:0] encoding;
// Build enable mask by iterating through every input bit.
for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit
assign encoding[n] = n[m];
end
// OR tree for this output bit with appropraite bits enabled.
assign out[m] = |(encoding & in);
end
endgenerate
endmodule // binary_encoder
lib/control/cvita_uart.v
+13 -1
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@@ -2,7 +2,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//create a compressed vita based uart data interface
lib/control/gpio_atr.v
+13 -1
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@@ -2,7 +2,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module gpio_atr
lib/control/por_gen.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module por_gen
lib/control/ram_2port.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/control/reset_sync.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/control/serial_to_settings.v
+111
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@@ -0,0 +1,111 @@
module serial_to_settings
(
input clk,
input reset,
// Serial signals (async)
input scl,
input sda,
// Settngs bus out
output reg set_stb,
output reg [7:0] set_addr,
output reg [31:0] set_data
);
reg [2:0] state;
localparam SEARCH = 3'h0;
localparam ADDRESS = 3'h1;
localparam DATA = 3'h2;
localparam STOP1 = 3'h3;
localparam STOP2 = 3'h4;
reg scl_pre_reg, scl_reg, scl_reg2;
reg sda_pre_reg, sda_reg, sda_reg2;
reg [4:0] counter;
always @(posedge clk) begin
scl_reg2 <= scl_reg;
scl_reg <= scl_pre_reg;
scl_pre_reg <= scl;
sda_reg2 <= sda_reg;
sda_reg <= sda_pre_reg;
sda_pre_reg <= sda;
end
always @(posedge clk)
if (reset) begin
state <= SEARCH;
counter <= 0;
set_addr <= 0;
set_data <= 0;
set_stb <= 0;
end else begin
case(state)
//
// Search for I2C like start indication: SDA goes low whilst clock is high.
//
SEARCH: begin
set_stb <= 0;
// Look for START.
if (scl_reg && scl_reg2 && !sda_reg && sda_reg2) begin
state <= ADDRESS;
counter <= 0;
end
end
//
// Count 8 Address bits.
// Master changes SDA on falling edge of SCL, we sample on the rising edge.
//
ADDRESS: begin
if (scl_reg && !scl_reg2) begin
set_addr[7:0] <= {set_addr[6:0],sda_reg};
if (counter == 7) begin
state <= DATA;
counter <= 0;
end else
counter <= counter + 1;
end
end
//
// Count 32 data bits.
// Master changes SDA on falling edge of SCL, we sample on the rising edge.
//
DATA: begin
if (scl_reg && !scl_reg2) begin
set_data[31:0] <= {set_data[30:0],sda_reg};
if (counter == 31) begin
state <= STOP1;
counter <= 0;
end else
counter <= counter + 1;
end
end
//
// Looks for rising SCL edge before STOP bit.
//
STOP1: begin
if (scl_reg && !scl_reg2) begin
state <= STOP2;
end
end
//
// Looks for STOP bit
//
STOP2: begin
if (scl_reg && scl_reg2 && sda_reg && !sda_reg2) begin
state <= SEARCH;
counter <= 0;
set_stb <= 1;
end
end
endcase // case(state)
end // else: !if(reset)
endmodule // serial_to_settings
lib/control/serial_to_settings_tb.v
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@@ -0,0 +1,54 @@
module serial_to_settings_tb();
reg clk;
reg reset;
wire scl;
wire sda;
wire set_stb;
wire [7:0] set_addr;
wire [31:0] set_data;
//
// These registers optionaly used
// to drive nets through procedural assignments in test bench.
// These drivers default to tri-stated.
//
reg scl_r;
reg sda_r;
assign scl = scl_r;
assign sda = sda_r;
initial
begin
scl_r <= 1'bz;
sda_r <= 1'bz;
end
serial_to_settings serial_to_settings_i
(
.clk(clk),
.reset(reset),
// Serial signals (async)
.scl(scl),
.sda(sda),
// Settngs bus out
.set_stb(set_stb),
.set_addr(set_addr),
.set_data(set_data)
);
//
// Bring in a simulation script here
//
`include "simulation_script.v"
endmodule
lib/control/setting_reg.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//----------------------------------------------------------------------
//-- A settings register is a peripheral for the settings register bus.
lib/control/settings_bus_crossclock.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/control/simple_i2c_core.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Simple I2C core
lib/control/simple_spi_core.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Simple SPI core, the simplest, yet complete spi core I can think of
lib/dsp/acc.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module acc
lib/dsp/add2.v
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module add2
lib/dsp/add2_and_round.v
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module add2_and_round
lib/dsp/add2_and_round_reg.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module add2_and_round_reg
lib/dsp/add2_reg.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module add2_reg
lib/dsp/cic_dec_shifter.v
+13 -1
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
lib/dsp/cic_decim.v
+13 -1
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
lib/dsp/cic_int_shifter.v
+13 -1
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
lib/dsp/cic_interp.v
+13 -1
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
lib/dsp/cic_strober.v
+13 -1
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@@ -3,7 +3,19 @@
//
// Copyright (C) 2008 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_strober
lib/dsp/clip.v
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//
// Copyright (C) 2008 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Clipping "macro", keeps the bottom bits
lib/dsp/clip_reg.v
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2008 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Clipping "macro", keeps the bottom bits
lib/dsp/cordic_stage.v
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//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
lib/dsp/cordic_z24.v
+13 -1
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2003, 2007 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo );
lib/dsp/ddc_chain.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//! The USRP digital down-conversion chain
lib/dsp/duc_chain.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//! The USRP digital up-conversion chain
lib/dsp/hb_dec.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Final halfband decimator
// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
lib/dsp/hb_interp.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// First halfband iterpolator
// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
lib/dsp/round.v
+13 -1
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2011 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Rounding "macro"
lib/dsp/round_reg.v
+13 -1
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2008 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Rounding "macro"
lib/dsp/rx_dcoffset.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/dsp/sign_extend.v
+13 -1
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@@ -4,7 +4,19 @@
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
lib/dsp/small_hb_dec.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Short halfband decimator (intended to be followed by another stage)
// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
lib/dsp/small_hb_int.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Short halfband decimator (intended to be followed by another stage)
// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
lib/dsp/srl.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module srl
lib/fifo/axi_fifo.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Block RAM AXI fifo
lib/fifo/axi_fifo_2clk.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Special case SIZE <= 5 uses a short fifo
lib/fifo/axi_fifo_short.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// 32 word FIFO with AXI4-STREAM interface.
lib/fifo/axi_packet_gate.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Hold packets in fifo until they are complete. This prevents slowly-built packets
// from clogging up the downstream. This block will hold up to 255 packets.
lib/fifo/monitor_axi_fifo.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// This module is instantiated in parallel with a FIFO with AXI4-STREAM interfaces.
lib/fifo/shortfifo.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module shortfifo
lib/gpif2/fifo64_to_gpif2.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module fifo64_to_gpif2
#(
lib/gpif2/gpif2_slave_fifo32.v
+44 -83
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@@ -1,7 +1,19 @@
//
// Copyright 2011-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
@@ -23,8 +35,11 @@ module gpif2_slave_fifo32
parameter END_WITH_COMMA = 0
)
(// GPIF signals
input gpif_clk, input gpif_rst, input gpif_enb,
(
// GPIF signals
input gpif_clk,
input gpif_rst,
input gpif_enb,
inout [31:0] gpif_d,
input [3:0] gpif_ctl,
output reg sloe,
@@ -33,15 +48,18 @@ module gpif2_slave_fifo32
output slcs,
output reg pktend,
output reg [1:0] fifoadr,
// FIFO interfaces
input fifo_clk, input fifo_rst,
input fifo_clk,
input fifo_rst,
// TX Data interface to DSP
output [63:0] tx_tdata, output tx_tlast, output tx_tvalid, input tx_tready,
// RX Data interface to DSP
input [63:0] rx_tdata, input rx_tlast, input rx_tvalid, output rx_tready,
// Incomming control interface
output [63:0] ctrl_tdata, output ctrl_tlast, output ctrl_tvalid, input ctrl_tready,
// Outgoing control interface
input [63:0] resp_tdata, input resp_tlast, input resp_tvalid, output resp_tready,
// Debug Signals
output [31:0] debug
);
@@ -49,8 +67,6 @@ module gpif2_slave_fifo32
wire ctrl_tx_fifo_nearly_full, data_tx_fifo_nearly_full;
wire ctrl_tx_fifo_has_space, data_tx_fifo_has_space;
wire [159:0] debug_tx_data, debug_tx_ctrl;
assign slcs = 1'b0;
@@ -137,14 +153,19 @@ module gpif2_slave_fifo32
end
//
// now wait here for 8 clock cycles before transitioning to STATE_THINK.
// We stay in this state if no local FIFO's can proceed at this point.
// If the current thread we are pointing at (fifoadr) can not immediately proceed
// then quickly move to the next thread. Once we are pointing at a thread that can proceed locally
// wait for 8 clock cycles to allow fifoadr to propogate to FX3, and corresponding flag state to
// propogate back to FPGA and through resampling flops. At this point transition to STATE_THINK
// to evaluate remote flag.
//
STATE_WAIT: begin
// Current thread can proceed locally
if (local_fifo_ready) begin
idle_cycles <= idle_cycles + 1'b1;
if (idle_cycles == 3'b111) state <= STATE_THINK;
end
// ....move onto next thread.
else begin
idle_cycles <= 3'b0;
fifoadr <= fifoadr + 2'b1;
@@ -154,10 +175,10 @@ module gpif2_slave_fifo32
//
// If there is a read to start, assert SLRD and SLOE and transition to STATE_READ.
// If there is a write to perform, set flags that says there is the possibility to do at least
// one write (wr_one) and transition to STATE_WRITE
// one write (wr_one) and transition to STATE_WRITE.
// If the FX3 has nothing ready for this thread return immediately to STATE_IDLE.
//
STATE_THINK: begin
if (EP_READY1 && read_ready_go) begin
state <= STATE_READ;
slrd <= 0;
@@ -215,13 +236,17 @@ module gpif2_slave_fifo32
//Priority encoding for the the next address to service:
//The next address to service is based on the readiness
//of the internal fifos and last serviced fairness metric.
/* -----\/----- EXCLUDED -----\/-----
always @(posedge gpif_clk) next_addr <=
((ctrl_rx_tvalid && last_addr != ADDR_CTRL_RX)? ADDR_CTRL_RX :
((ctrl_tx_fifo_has_space && last_addr != ADDR_CTRL_TX)? ADDR_CTRL_TX :
((data_rx_tvalid && last_addr != ADDR_DATA_RX)? ADDR_DATA_RX :
((data_tx_fifo_has_space && last_addr != ADDR_DATA_TX)? ADDR_DATA_TX :
((ctrl_rx_tvalid && (last_addr != ADDR_CTRL_RX))? ADDR_CTRL_RX :
((ctrl_tx_fifo_has_space && (last_addr != ADDR_CTRL_TX))? ADDR_CTRL_TX :
((data_rx_tvalid && (last_addr != ADDR_DATA_RX))? ADDR_DATA_RX :
((data_tx_fifo_has_space && (last_addr != ADDR_DATA_TX))? ADDR_DATA_TX :
(fifoadr + 2'b1)
))));
-----/\----- EXCLUDED -----/\----- */
always @(posedge gpif_clk) next_addr <= (fifoadr + 2'b1);
//Help the FPGA search to only look for addrs that the FPGA is ready for
assign local_fifo_ready =
@@ -268,7 +293,7 @@ module gpif2_slave_fifo32
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
.fifo_nearly_full(data_tx_fifo_nearly_full), .fifo_has_space(data_tx_fifo_has_space),
.o_tdata(tx_tdata), .o_tlast(tx_tlast), .o_tvalid(tx_tvalid), .o_tready(tx_tready),
.bus_error(tx_bus_error), .debug(debug_tx_data)
.bus_error(tx_bus_error), .debug()
);
// ////////////////////////////////////////////
@@ -290,7 +315,7 @@ module gpif2_slave_fifo32
.fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
.fifo_nearly_full(ctrl_tx_fifo_nearly_full), .fifo_has_space(ctrl_tx_fifo_has_space),
.o_tdata(ctrl_tdata), .o_tlast(ctrl_tlast), .o_tvalid(ctrl_tvalid), .o_tready(ctrl_tready),
.bus_error(ctrl_bus_error), .debug(debug_tx_ctrl)
.bus_error(ctrl_bus_error), .debug()
);
// ////////////////////////////////////////////////////////////////////
@@ -306,70 +331,6 @@ module gpif2_slave_fifo32
// ////////////////////////////////////////////
// DEBUG
wire [31:0] debug0 = {
sloe, slrd, slwr, pktend, fifoadr, EP_READY, EP_WMARK, //8
state, //4
data_tx_tvalid, data_tx_tready, data_rx_tvalid, data_rx_tready, //4
gpif_d[15:0] //16
};
reg [31:0] debug_reg0;
reg [31:0] debug_reg1;
reg [31:0] debug_reg2;
always @(posedge gpif_clk) debug_reg0 <= debug0;
always @(posedge gpif_clk) debug_reg1 <= debug_reg0;
always @(posedge gpif_clk) debug_reg2 <= debug_reg1;
assign debug = debug_reg2;
wire [37:0] debug_resp = {
resp_tlast, // 37
resp_tready, // 36
resp_tvalid, // 35
ctrl_rx_tlast, // 34
ctrl_rx_tready, // 33
ctrl_rx_tvalid, // 32
ctrl_rx_tdata // 31:0
};
reg [255:0] debug1,debug2;
always @(posedge gpif_clk) debug1 <= {debug_resp,debug_tx_ctrl,debug0};
always @(posedge gpif_clk) debug2 <= debug1;
wire [35:0] CONTROL0,CONTROL1;
/*
chipscope_ila_32 chipscope_ila_32(
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(gpif_clk), // IN
.TRIG0(debug2) // IN BUS [31:0]
);
chipscope_ila_128 chipscope_ila_128(
.CONTROL(CONTROL1), // INOUT BUS [35:0]
.CLK(fifo_clk), // IN
.TRIG0({debug4,debug6}) // IN BUS [31:0]
);
chipscope_ila_256 chipscope_ila_256(
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(gpif_clk), // IN
.TRIG0(debug2) // IN BUS [31:0]
);
chipscope_ila_32 chipscope_ila_32_2(
.CONTROL(CONTROL1), // INOUT BUS [35:0]
.CLK(gpif_clk), // IN
.TRIG0(32'd0) // IN BUS [31:0]
);
chipscope_icon chipscope_icon(
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
);
*/
endmodule // gpif2_slave_fifo32
lib/gpif2/gpif2_to_fifo64.v
+122 -104
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@@ -1,118 +1,136 @@
//
// Copyright 2012-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module gpif2_to_fifo64
#(
#(
parameter FIFO_SIZE = 9
)
(
//input interface
input gpif_clk, input gpif_rst,
input [31:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output fifo_has_space,
output fifo_nearly_full,
//output fifo interface
input fifo_clk, input fifo_rst,
output [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready,
output bus_error,
output [159:0] debug
);
wire [31:0] int_tdata;
wire int_tlast;
wire int_tvalid, int_tready;
wire [31:0] int0_tdata; wire int0_tlast, int0_tvalid, int0_tready;
//this fifo provides a space signal so we know a burst is possible
localparam BURST_SIZE = (FIFO_SIZE < 8)? FIFO_SIZE : 8;
wire [15:0] space;
assign fifo_has_space = space >= (1 << BURST_SIZE);
assign fifo_nearly_full = (space < 6); // 5 spaces left.
axi_fifo #(.WIDTH(33), .SIZE(0)) ingress_timing_fifo
)
(
.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
.i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), .space(),
.o_tdata({int0_tlast, int0_tdata}), .o_tvalid(int0_tvalid), .o_tready(int0_tready), .occupied()
);
axi_fifo #(.WIDTH(33), .SIZE(BURST_SIZE)) min_read_buff
(
.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
.i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(space),
.o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready), .occupied()
);
reg input_write_error;
always @(posedge gpif_clk) input_write_error <= i_tvalid & ~i_tready;
//input interface
input gpif_clk,
input gpif_rst,
input [31:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output fifo_has_space,
output fifo_nearly_full,
//output fifo interface
input fifo_clk,
input fifo_rst,
output [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready,
output bus_error,
output [31:0] debug
);
wire [31:0] int_tdata;
wire int_tlast;
wire int_tvalid, int_tready;
wire [31:0] int0_tdata;
wire int0_tlast, int0_tvalid, int0_tready;
//
// Generate flags that show if initial FIFO's can accept a maximum sized burst from the FX3
// or if the FIFO is about to fill.
//
localparam BURST_SIZE = (FIFO_SIZE < 8)? FIFO_SIZE : 8;
wire [15:0] space;
assign fifo_has_space = space >= (1 << BURST_SIZE);
assign fifo_nearly_full = (space < 6); // 5 spaces left.
//
// This FIFO is provdied purely to easy FPGA timing closure as data is comming from I/O pins.
//
axi_fifo #(.WIDTH(33), .SIZE(0)) ingress_timing_fifo
(
.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
.i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), .space(),
.o_tdata({int0_tlast, int0_tdata}), .o_tvalid(int0_tvalid), .o_tready(int0_tready), .occupied()
);
//
// This FIFO provides space to accept a single burst from FX3 and it's fullness drives flags to GPIF2 logic
//
axi_fifo #(.WIDTH(33), .SIZE(BURST_SIZE)) min_read_buff
(
.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
.i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(space),
.o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready), .occupied()
);
//
// This logic allows signals to cross from the GPIF2 clock domain to the BUS clock domain.
// It may now be obselete if bus_clk and gpif_clk are merged
//
wire [31:0] chk_tdata;
wire chk_tlast;
wire chk_tvalid, chk_tready;
axi_fifo_2clk #(.WIDTH(33), .SIZE(0/*SRL*/)) cross_clock_fifo
(
.reset(fifo_rst | gpif_rst),
.i_aclk(gpif_clk), .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready),
.o_aclk(fifo_clk), .o_tdata({chk_tlast, chk_tdata}), .o_tvalid(chk_tvalid), .o_tready(chk_tready)
);
//
// Performs basic tests on incomming packets such as testing if size on the wire patches
// the internal size field. Uses axi_packet_gate internally so can back pressure upstream if
// packet needs to be dropped.
//
wire [31:0] o32_tdata;
wire o32_tlast;
wire o32_tvalid, o32_tready;
gpif2_error_checker #(.SIZE(FIFO_SIZE)) checker
(
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.i_tdata(chk_tdata), .i_tlast(chk_tlast), .i_tvalid(chk_tvalid), .i_tready(chk_tready),
.o_tdata(o32_tdata), .o_tlast(o32_tlast), .o_tvalid(o32_tvalid), .o_tready(o32_tready),
.bus_error(bus_error), .debug()
);
//assign o32_tdata = chk_tdata;
//assign o32_tlast = chk_tlast;
//assign o32_tvalid = chk_tvalid;
//assign chk_tready = o32_tready;
wire [31:0] chk_tdata;
wire chk_tlast;
wire chk_tvalid, chk_tready;
//
// Convert 32bit AXIS bus to 64bit
//
axi_fifo32_to_fifo64 fifo32_to_fifo64
(
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.i_tdata(o32_tdata), .i_tuser(2'b0/*always 32 bits*/), .i_tlast(o32_tlast), .i_tvalid(o32_tvalid), .i_tready(o32_tready),
.o_tdata(o_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
);
axi_fifo_2clk #(.WIDTH(33), .SIZE(0/*SRL*/)) cross_clock_fifo
(
.reset(fifo_rst | gpif_rst),
.i_aclk(gpif_clk), .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready),
.o_aclk(fifo_clk), .o_tdata({chk_tlast, chk_tdata}), .o_tvalid(chk_tvalid), .o_tready(chk_tready)
);
wire [31:0] o32_tdata;
wire o32_tlast;
wire o32_tvalid, o32_tready;
/////////////////////////////////////////////
//
// Debug logic only
//
/////////////////////////////////////////////
//reframes a tlast from the vita header - and drops bad packets
//*
gpif2_error_checker #(.SIZE(FIFO_SIZE)) checker
(
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.i_tdata(chk_tdata), .i_tlast(chk_tlast), .i_tvalid(chk_tvalid), .i_tready(chk_tready),
.o_tdata(o32_tdata), .o_tlast(o32_tlast), .o_tvalid(o32_tvalid), .o_tready(o32_tready),
.bus_error(bus_error), .debug(debug[63:0])
);
//*/
//assign o32_tdata = chk_tdata;
//assign o32_tlast = chk_tlast;
//assign o32_tvalid = chk_tvalid;
//assign chk_tready = o32_tready;
axi_fifo32_to_fifo64 fifo32_to_fifo64
(
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.i_tdata(o32_tdata), .i_tuser(2'b0/*always 32 bits*/), .i_tlast(o32_tlast), .i_tvalid(o32_tvalid), .i_tready(o32_tready),
.o_tdata(o_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
);
assign debug[159:64] = {
fifo_nearly_full, // 146
space[9:0], // 145:136
input_write_error, // 135
int_tlast, // 134
int_tready, // 133
int_tvalid, // 132
i_tlast, // 131
i_tready, // 130
fifo_has_space, // 129
i_tvalid, // 128
int_tdata[31:0], // 127:96
i_tdata[31:0] // 95:64
};
endmodule //fifo_to_gpif2
lib/packet_proc/cvita_chunker.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Quantize cvita packets to a configurable quantum value. o_tlast and
// i_tready will be held off until the entire quantized packet is xferred.
// If quantum is changed, it is the responsibility of the client to clear
lib/packet_proc/cvita_chunker_tb.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 500ps/1ps
lib/packet_proc/cvita_dechunker.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module cvita_dechunker # (
parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
lib/packet_proc/cvita_dechunker_tb.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 500ps/1ps
lib/packet_proc/eth_dispatch.v
+12 -8
View File
@@ -72,6 +72,7 @@ module eth_dispatch
output xo_tvalid,
input xo_tready,
// Debug
output [2:0] debug_flags,
output [31:0] debug
);
@@ -93,6 +94,7 @@ module eth_dispatch
//
// Small RAM stores packet header during parsing.
//
// IJB consider changing HEADER_RAM_SIZE to 7
localparam HEADER_RAM_SIZE = 9;
(*ram_style="distributed"*)
reg [68:0] header_ram [HEADER_RAM_SIZE-1:0];
@@ -100,7 +102,7 @@ module eth_dispatch
reg drop_this_packet;
wire header_done = (header_ram_addr == HEADER_RAM_SIZE-1);
reg fwd_input;
reg fwd_input;
//
reg [63:0] in_tdata_reg;
@@ -112,10 +114,8 @@ module eth_dispatch
wire [3:0] out_tuser;
wire [63:0] out_tdata;
//
// Output AXI-STream interface to VITA Radio Core
// Output AXI-Stream interface to VITA Radio Core
wire [63:0] vita_pre_tdata;
wire [3:0] vita_pre_tuser;
wire vita_pre_tlast;
@@ -147,10 +147,6 @@ module eth_dispatch
reg is_icmp_no_fwd;
reg is_chdr;
//
// Settings regs
//
@@ -417,12 +413,14 @@ module eth_dispatch
end
7: begin
// Look for a possible CHDR header string
// IJB. NOTE this is not a good test for a CHDR packet, we perhaps don;t need this state anyhow.
if (in_tdata_reg[63:32] != 32'h0)
is_chdr <= 1'b1;
end
8: begin
// Check VRT Stream ID
// ADD THIS HERE.
// IJB. Perhaps delete this state.
end
endcase // case (header_ram_addr)
end // if (in_tvalid && in_tready)
@@ -452,9 +450,12 @@ module eth_dispatch
(out_tready && fwd_input);
//
// Because we can forward to both the ZPU and XO FIFO's concurrently
// we have to make sure both can accept data in the same cycle.
// This makes it possible for either destination to block the other.
// Make sure (both) destination(s) can accept data before passing it.
//
assign xo_pre_tvalid = out_tvalid &&
((state == FORWARD_XO) ||
((state == FORWARD_ZPU_AND_XO) && zpu_pre_tready));
@@ -524,6 +525,9 @@ module eth_dispatch
.space(),
.occupied()
);
assign debug_flags = {vita_pre_tready,xo_pre_tready,zpu_pre_tready};
/* -----\/----- EXCLUDED -----\/-----
lib/packet_proc/eth_dispatch_tb.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1 ps / 1 ps
module eth_dispatch_tb();
lib/packet_proc/eth_interface.v
+51 -4
View File
@@ -21,7 +21,8 @@ module eth_interface
// ZPU
output [63:0] e2z_tdata, output [3:0] e2z_tuser, output e2z_tlast, output e2z_tvalid, input e2z_tready,
input [63:0] z2e_tdata, input [3:0] z2e_tuser, input z2e_tlast, input z2e_tvalid, output z2e_tready,
// Debug
output [31:0] debug_flags,
output [31:0] debug
);
@@ -36,7 +37,12 @@ module eth_interface
wire [63:0] epg_tdata_int;
wire [3:0] epg_tuser_int;
wire epg_tlast_int, epg_tvalid_int, epg_tready_int;
//
// Packet gate ensures on entire ingressing packet is buffered before feeding it downstream so that it bursts
// efficiently internally without holding resources allocted for longer than optimal. This also means that an upstream
// error discovered in the packet can allow the packet to be destroyed here, before it gets deeper into the USRP.
//
axi_packet_gate #(.WIDTH(68), .SIZE(10)) packet_gater //holds 8K pkts
(.clk(clk), .reset(reset), .clear(clear),
@@ -47,10 +53,14 @@ module eth_interface
.o_tdata({epg_tuser_int, epg_tdata_int}), .o_tlast(epg_tlast_int),
.o_tvalid(epg_tvalid_int), .o_tready(epg_tready_int));
//
// Based on programmed rules, parse network headers and decide which internal destination(s) this packet will be forwarded to.
//
wire [63:0] e2z_tdata_int;
wire [3:0] e2z_tuser_int;
wire e2z_tlast_int, e2z_tvalid_int, e2z_tready_int;
wire [2:0] dispatch_debug_flags;
eth_dispatch #(.BASE(BASE+8)) eth_dispatch
(.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data),
@@ -58,8 +68,11 @@ module eth_interface
.vita_tdata(e2v_tdata), .vita_tlast(e2v_tlast), .vita_tvalid(e2v_tvalid), .vita_tready(e2v_tready),
.zpu_tdata(e2z_tdata_int), .zpu_tuser(e2z_tuser_int), .zpu_tlast(e2z_tlast_int), .zpu_tvalid(e2z_tvalid_int), .zpu_tready(e2z_tready_int),
.xo_tdata(xo_tdata), .xo_tuser(xo_tuser), .xo_tlast(xo_tlast), .xo_tvalid(xo_tvalid), .xo_tready(xo_tready), // to other eth port
.debug(debug));
.debug_flags(dispatch_debug_flags),.debug(debug));
//
// ZPU can be slow to respond (relative to packet wirespeed) so extra buffer for packets destined there so it doesn't back up.
//
axi_fifo #(.WIDTH(69),.SIZE(ZPU_FIFOSIZE)) zpu_fifo
(.clk(clk), .reset(reset), .clear(clear),
.i_tdata({e2z_tlast_int,e2z_tuser_int,e2z_tdata_int}), .i_tvalid(e2z_tvalid_int), .i_tready(e2z_tready_int),
@@ -110,4 +123,38 @@ module eth_interface
.i_tdata({eth_tx_tlast_int,eth_tx_tuser_int,eth_tx_tdata_int}), .i_tvalid(eth_tx_tvalid_int), .i_tready(eth_tx_tready_int),
.o_tdata({eth_tx_tlast,eth_tx_tuser,eth_tx_tdata}), .o_tvalid(eth_tx_tvalid), .o_tready(eth_tx_tready));
//
// Provide instrumentation so that abnormal FIFO conditions can be identifed.
//
/* -----\/----- EXCLUDED -----\/-----
setting_reg #(.my_addr(BASE+15), .awidth(16), .width(1)) sr_reset_fifo_debug
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_debug_flags));
always @(posedge clk)
if (reset)
debug_flags <= 0;
else if (clear_debug_flags)
debug_flags <= 0;
else
debug_flags <= debug_flags | {eth_rx_tuser[3],
~eth_tx_tready_int,
~xi_tready,
~v2e_tready,
~e2z_tready_int,
~eth_rx_tready,
~dispatch_debug_flags[2:0]};
-----/\----- EXCLUDED -----/\----- */
assign debug_flags = {eth_rx_tuser[3],
~eth_tx_tready_int,
~xi_tready,
~v2e_tready,
~e2z_tready_int,
~eth_rx_tready,
~dispatch_debug_flags[2:0]};
endmodule // eth_interface
lib/timing/time_compare.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// 64 bits worth of ticks
lib/timing/time_transfer_tb.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1ns / 1ps
lib/timing/timekeeper.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module timekeeper
#(parameter BASE = 0)
lib/vita/chdr_12sc_to_16sc.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/vita/chdr_16sc_to_12sc.v
+219 -180
View File
@@ -1,221 +1,260 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module chdr_16sc_to_12sc
#(parameter BASE=0)
( input set_stb, input [7:0] set_addr, input [31:0] set_data,
//left side of device
input clk, input reset,
(
// Clocks and resets
input clk,
input reset,
// Settings bus
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
// Input CHDR bus
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
//right side of device
output reg [63:0] o_tdata = 0,
// Output CHDR bus
output reg [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready,
// Debug
output [31:0] debug
);
wire chdr_has_hdr = 1'b1;
wire chdr_has_time = i_tdata[61];
wire chdr_has_tlr = 1'b0;
);
wire [11:0] imag0;
wire [11:0] real0;
wire [11:0] imag1;
wire [11:0] real1;
wire [11:0] imag2;
wire [11:0] real2;
wire chdr_has_time = i_tdata[61];
wire [16:0] round_i0;
wire [16:0] round_r0;
wire [16:0] round_i1;
wire [16:0] round_r1;
wire [16:0] round_i2;
wire [16:0] round_r2;
wire [11:0] q0;
wire [11:0] i0;
wire [11:0] q1;
wire [11:0] i1;
wire [11:0] q2;
wire [11:0] i2;
//pipiline registers
wire [16:0] round_q0;
wire [16:0] round_i0;
wire [16:0] round_q1;
wire [16:0] round_i1;
wire [16:0] round_q2;
wire [16:0] round_i2;
reg [11:0] imag0_out;
reg [11:0] real0_out;
reg [11:0] imag1_out;
reg [11:0] real1_out;
// Pipeline registers
reg [11:0] q0_out;
reg [11:0] i0_out;
reg [11:0] q1_out;
reg [11:0] i1_out;
reg [15:0] len_data;
// CHDR has either 8 bytes of header or 16 if VITA time is included.
wire [15:0] chdr_header_lines = chdr_has_time? 16 : 8;
// Calculate size of samples input in bytes by taking CHDR size filed and subtracting header length.
wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_lines;
// Calculate size of samples to be output by taking input size and scaling by 3/4
wire [15:0] sample_byte_count_out = (sample_byte_count_in*3) >> 2;
// Calculate size of output CHDR packet by adding back header size to new payload size.
wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_lines;
//chdr length calculations
wire [15:0] chdr_header_lines = chdr_has_time? 16 : 8;
wire [15:0] in_samples = i_tdata[47:32] - chdr_header_lines;
wire [15:0] samples = (in_samples*3) >> 2;
wire [15:0] chdr_payload_lines = samples + chdr_header_lines;
reg needs_extra_line;
reg in_extra_line;
wire set_sid;
wire [15:0] new_sid_dst;
reg needs_exline = 0;
reg in_exline = 0;
wire set_sid;
wire [15:0] my_newhome;
setting_reg #(.my_addr(BASE), .width(17)) new_destination
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out({set_sid, my_newhome[15:0]}));
//state machine
.out({set_sid, new_sid_dst[15:0]}));
// state machine
localparam HEADER = 3'd0; // IDLE
localparam TIME = 3'd1;
localparam LINE_ODD_ZERO = 3'd2;
localparam LINE_EVEN_ONE = 3'd3;
localparam LINE_ODD_TWO = 3'd4;
localparam REG_STATE = 3'd5;
reg [2:0] state;
always @(posedge clk) begin
if (reset) begin
state <= HEADER;
needs_exline <= 0;
in_exline <= 0;
end
localparam HEADER = 3'd0;
localparam TIME = 3'd1;
localparam SAMPLE1 = 3'd2;
localparam SAMPLE2 = 3'd3;
localparam SAMPLE3 = 3'd4;
localparam SAMPLE4 = 3'd5;
else if ((o_tvalid && o_tready) || (i_tready && i_tvalid)) case(state)
reg [2:0] state;
HEADER: begin
needs_exline <= (in_samples[4:2] == 3 || in_samples[4:2] == 4 || in_samples[4:2] == 6);
state <= (i_tdata[61])? TIME: REG_STATE;
end
always @(posedge clk)
if (reset) begin
state <= HEADER;
needs_extra_line <= 0;
in_extra_line <= 0;
end else begin
case(state)
//
// Process Header line of input packet or idle in this state waiting for new packet.
// If the the input packet has SAMPLE_COUNT MODULO 8 == 3 or 4 or 6 then when tlast is asserted we will need one more
// output cycle to finish outputing processed samples.
//
HEADER: begin
if (o_tready && i_tvalid)
begin
needs_extra_line <= (sample_byte_count_in[4:2] == 3 || sample_byte_count_in[4:2] == 4 || sample_byte_count_in[4:2] == 6);
// If the input packet had time, then add time to output packet
state <= (i_tdata[61])? TIME: SAMPLE1;
end
end
//
// Process time field of input packet
//
TIME: begin
if (o_tready && i_tvalid)
begin
// If we get a premature end of line go back to searching for start of new packet.
state <= (i_tlast) ? HEADER: SAMPLE1;
end
end
//
// Process line of sample data from input packet.
// Not yet enough data to prepare first of three repeating output lines
// unless this the last line of a packet when the lats output line
// is composed of data from one or both samples in this input packet.
//
SAMPLE1: begin
if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin
// We can finish this packet immediately.
state <= HEADER;
in_extra_line <= 0;
end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin
// We still need one more output line to drain all samples into this packet.
// (SHOULD NOT BE POSSIBLE TO GET HERE!)
state <= SAMPLE2;
in_extra_line <= 1;
end else if (o_tready && i_tvalid)
state <= SAMPLE2;
end
//
// First of three repeating output line patterns
//
SAMPLE2: begin
if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin
// We can finish this packet immediately.
state <= HEADER;
in_extra_line <= 0;
end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin
// We still need one more output line to drain all samples into this packet.
state <= SAMPLE3;
in_extra_line <= 1;
end else if (o_tready && i_tvalid)
state <= SAMPLE3;
end
//
// Second of three repeating output line patterns
//
SAMPLE3: begin
if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin
// We can finish this packet immediately.
state <= HEADER;
in_extra_line <= 0;
end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin
// We still need one more output line to drain all samples into this packet.
state <= SAMPLE4;
in_extra_line <= 1;
end else if (o_tready && i_tvalid)
state <= SAMPLE4;
end
//
// Third of three repeating output line patterns
//
SAMPLE4: begin
if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin
// We can finish this packet immediately.
state <= HEADER;
in_extra_line <= 0;
end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin
// We still need one more output line to drain all samples into this packet.
// (SHOULD NOT BE POSSIBLE TO GET HERE!!)
state <= SAMPLE1;
in_extra_line <= 1;
end else if (o_tready && i_tvalid)
state <= SAMPLE1;
end
//
// Should never get here.
//
default: state <= HEADER;
TIME: begin
state <= (i_tlast) ? HEADER: REG_STATE;
end
REG_STATE: begin
if (i_tlast & !needs_exline || in_exline) begin
state <= HEADER;
in_exline <= 0;
end
else if (i_tlast & needs_exline) begin
state <= LINE_EVEN_ONE;
in_exline <= 1;
end
else
state <= LINE_EVEN_ONE;
end
endcase
end
LINE_EVEN_ONE: begin
if (i_tlast & !needs_exline || in_exline) begin
state <= HEADER;
in_exline <= 0;
end
else if (i_tlast & needs_exline) begin
state <= LINE_ODD_TWO;
in_exline <= 1;
end
else
state <= LINE_ODD_TWO;
end
// Add rounding value into 16bit samples before trunctaion
assign round_q0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008);
assign round_i0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008);
// Truncate with saturation to 12bits precision.
assign q0 = (round_q0[16:15] == 2'b01) ? 12'h7FF : ((round_q0[16:15] == 2'b10) ? 12'h800 : round_q0[15:4]);
assign i0 = (round_i0[16:15] == 2'b01) ? 12'h7FF : ((round_i0[16:15] == 2'b10) ? 12'h800 : round_i0[15:4]);
// Add rounding value into 16bit samples before trunctaion
assign round_q1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008);
assign round_i1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008);
// Truncate with saturation to 12bits precision.
assign q1 = (round_q1[16:15] == 2'b01) ? 12'h7FF : ((round_q1[16:15] == 2'b10) ? 12'h800 : round_q1[15:4]);
assign i1 = (round_i1[16:15] == 2'b01) ? 12'h7FF : ((round_i1[16:15] == 2'b10) ? 12'h800 : round_i1[15:4]);
LINE_ODD_TWO: begin
if (i_tlast & !needs_exline || in_exline) begin
state <= HEADER;
in_exline <= 0;
end
else if (i_tlast & needs_exline) begin
state <= LINE_ODD_ZERO;
in_exline <= 1;
end
else
state <= LINE_ODD_ZERO;
end
LINE_ODD_ZERO: begin
if (i_tlast & !needs_exline || in_exline) begin
state <= HEADER;
in_exline <= 0;
end
else if (i_tlast & needs_exline) begin
state <= REG_STATE;
in_exline <= 1;
end
else
state <= REG_STATE;
end
default: state <= HEADER;
endcase
end
assign round_i0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008);
assign round_r0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008);
assign imag0 = (round_i0[16] == 0 && round_i0[15] == 1)?(12'h7FF):(round_i0[16] == 1 && round_i0[15] == 0)? (12'h800):(round_i0[15:4]);
assign real0 = (round_r0[16] == 0 && round_r0[15] == 1)?(12'h7FF):(round_r0[16] == 1 && round_r0[15] == 0)? (12'h800):(round_r0[15:4]);
assign round_i1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008);
assign round_r1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008);
assign imag1 = (round_i1[16] == 0 && round_i1[15] == 1)?(12'h7FF):(round_i1[16] == 1 && round_i1[15] == 0)? (12'h800):(round_i1[15:4]);
assign real1 = (round_r1[16] == 0 && round_r1[15] == 1)?(12'h7FF):(round_r1[16] == 1 && round_r1[15] == 0)? (12'h800):(round_r1[15:4]);
//
// Keep values from current input line to populate fields in next cycles output line
//
always @(posedge clk)
if (i_tvalid && o_tready)
begin
imag0_out <= imag0;
real0_out <= real0;
imag1_out <= imag1;
real1_out <= real1;
q0_out <= q0;
i0_out <= i0;
q1_out <= q1;
i1_out <= i1;
end
//
// Mux Output data
//
always @(*)
case(state)
HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
TIME: o_tdata <= i_tdata;
// Populate header with CHDR fields
HEADER: o_tdata = {i_tdata[63:48], output_chdr_pkt_size,
set_sid ? {i_tdata[15:0], new_sid_dst[15:0]}:i_tdata[31:0]};
// Add 64bit VITA time to packet
TIME: o_tdata = i_tdata;
// Special ending corner case for input packets with SAMPLE_COUNT MODULO 8 == (1 | 2)
SAMPLE1: o_tdata = {q0,i0,q1, i1, 16'b0};
// Line one of repeating 12bit packed data pattern
SAMPLE2: o_tdata = {q0_out, i0_out, q1_out, i1_out, q0, i0[11:8]};
// Line two of repeating 12bit packed data pattern
SAMPLE3: o_tdata = {i0_out[7:0], q1_out, i1_out, q0, i0,q1[11:4]};
// Line three of repeating 12bit packed data pattern
SAMPLE4: o_tdata = {q1_out[3:0], i1_out, q0, i0, q1, i1};
default : o_tdata = i_tdata;
endcase // case(state)
REG_STATE: o_tdata <= {imag0,real0,imag1, real1, 16'b0};
LINE_EVEN_ONE: o_tdata <= {imag0_out, real0_out, imag1_out, real1_out, imag0, real0[11:8]};
LINE_ODD_TWO: o_tdata <= {real0_out[7:0], imag1_out, real1_out, imag0, real0,imag1[11:4]};
LINE_ODD_ZERO: o_tdata <= {imag1_out[3:0], real1_out, imag0, real0, imag1, real1};
default : o_tdata <= i_tdata;
endcase
assign o_tvalid =((in_exline) || (state != REG_STATE & i_tvalid) || (i_tlast & i_tvalid & !needs_exline));
assign i_tready = (o_tready & !in_exline)||(state == REG_STATE && !i_tlast);
assign o_tlast = (needs_exline)? in_exline: i_tlast;
assign o_tvalid =
// We are outputing the (extra) last line of a packet
in_extra_line ||
// When not in the SAMPLE1 state and there's new input data (Unless its the last line....)
(state != SAMPLE1 & i_tvalid) ||
// Last line of input packet and we can finish this cycle. (Includes when state is SAMPLE1)
(i_tlast & i_tvalid & !needs_extra_line);
assign i_tready =
// Downstream is ready and we are not currently outputing last (extra) line of packet.
(o_tready && !in_extra_line) ||
// We don't create output data in SAMPLE1 unless its last line so don't need downstream ready to proceed.
((state == SAMPLE1) && !i_tlast);
assign o_tlast = (needs_extra_line) ? in_extra_line : i_tlast;
endmodule
lib/vita/chdr_16sc_to_32f.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/vita/chdr_16sc_to_xxxx_chain.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//selectable conversion chain
lib/vita/chdr_32f_to_16sc.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module chdr_32f_to_16sc
lib/vita/chdr_xxxx_to_16sc_chain.v
+13 -1
View File
@@ -2,7 +2,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//selectable conversion chain
lib/vita/new_rx_control.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// HALT brings RX to an idle state as quickly as possible if RX is running
// without running the risk of leaving a packet fragment in downstream FIFO's.
lib/vita/new_rx_framer.v
+12 -4
View File
@@ -1,6 +1,10 @@
module new_rx_framer
#(parameter BASE=0)
#(
parameter BASE=0,
parameter CHIPSCOPE=0,
parameter SAMPLE_FIFO_SIZE=10
)
(input clk, input reset, input clear,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -108,7 +112,7 @@ module new_rx_framer
endcase // case (instate)
always @(posedge clk)
if(strobe)
if(strobe && run)
begin
holding <= sample;
if(instate == 0)
@@ -119,7 +123,7 @@ module new_rx_framer
if(reset | clear)
len <= 5;
else
if(strobe)
if(strobe && run)
if(sample_tlast)
len <= 5;
else
@@ -146,7 +150,7 @@ module new_rx_framer
wire hdr_tready;
axi_fifo #(.WIDTH(65), .SIZE(10)) datafifo
axi_fifo #(.WIDTH(65), .SIZE(SAMPLE_FIFO_SIZE)) datafifo
(.clk(clk), .reset(reset), .clear(clear),
.i_tdata({sample_tlast,sample_tdata}), .i_tvalid(sample_tvalid), .i_tready(sample_tready),
.o_tdata({dfifo_tlast,dfifo_tdata}), .o_tvalid(dfifo_tvalid), .o_tready(dfifo_tready),
@@ -209,11 +213,15 @@ module new_rx_framer
.i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
.o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
.space(), .occupied());
/* -----\/----- EXCLUDED -----\/-----
assign debug[3:0] = {instate, outstate};
assign debug[7:4] = {1'b0, sample_tlast, sample_tvalid, sample_tready};
assign debug[11:8] = {1'b0, 1'b0, hfifo_tvalid, hfifo_tready};
assign debug[15:12] = {1'b0, dfifo_tlast, dfifo_tvalid, dfifo_tready};
assign debug[19:16] = {1'b0, o_tlast_int, o_tvalid_int, o_tready_int};
-----/\----- EXCLUDED -----/\----- */
endmodule // new_rx_framer
lib/vita/new_tx_control.v
+3 -2
View File
@@ -153,7 +153,8 @@ module new_tx_control
assign packet_consumed = eop & sample_tvalid & sample_tready;
assign debug = {
error_code[15:0], // [28:13]
error_code[37:32], // [30:25]
error_code[11:0], // [24:13]
sample_tvalid, //[12]
now, // [11]
early, // [10]
@@ -164,7 +165,7 @@ module new_tx_control
eob, // [5]
send_at, // [4]
odd, // [3]
state // [2:0]
state[2:0] // [2:0]
};
lib/vita/trigger_context_pkt.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/wishbone/axi_stream_to_wb.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// AXI stream to/from wishbone
// Input is an axi stream which wites into a BRAM.
lib/wishbone/settings_bus.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock
lib/wishbone/settings_readback.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// Use this module in conjunction with settings_bus.v to add stateful reads
lib/wishbone/simple_uart.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module simple_uart
lib/wishbone/simple_uart_rx.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2011-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
lib/wishbone/simple_uart_tx.v
+13 -1
View File
@@ -1,7 +1,19 @@
//
// Copyright 2011-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module simple_uart_tx
top/b200/b200.v
+35 -37
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
/***********************************************************
* B200 Module Declaration
@@ -23,8 +35,8 @@ module b200 (
output pll_sclk,
// UART
input FPGA_RXD0,
input FPGA_TXD0,
input FPGA_RXD0, // These pins goto 3 pin 0.1" header on B2x0 and
output FPGA_TXD0, // carry FX3 UART.
// Catalina Controls
output codec_enable,
@@ -63,8 +75,8 @@ module b200 (
output GPIF_CTL7, // n_pktend
input GPIF_CTL4, // slfifo_flags[0]
input GPIF_CTL5, // slfifo_flags[1]
input GPIF_CTL6, // slfifo_flags[2]
input GPIF_CTL8, // slfifo_flags[3]
input GPIF_CTL6, // Serial settings bus from FX3. SDA
input GPIF_CTL8, // Serial settings bus from FX3. SCL
output GPIF_CTL11, // slfifo_addr[1]
output GPIF_CTL12, // slfifo_addr[0]
inout [31:0] GPIF_D,
@@ -122,10 +134,14 @@ module b200 (
b200_clk_gen gen_clks
(
.CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n),
.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(bus_clk),
.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(),
.RESET(reset_global), .LOCKED(locked)
);
// Bus Clock and GPIF Clock both same 100MHz clock.
assign bus_clk = gpif_clk;
//hold-off logic for clocks ready
reg [15:0] clocks_ready_count;
reg clocks_ready;
@@ -193,32 +209,10 @@ module b200 (
wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid;
wire ctrl_tready, resp_tready, rx_tready, tx_tready;
///////////////////////////////////////////////////////////////////////
// loopback testers
///////////////////////////////////////////////////////////////////////
/*
axi_fifo #(.WIDTH(65), .SIZE(13)) f0
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({ctrl_tlast, ctrl_tdata}), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .space(),
.o_tdata({resp_tlast, resp_tdata}), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .occupied()
);
//*/
/*
axi_fifo #(.WIDTH(65), .SIZE(13)) f1
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .space(),
.o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .occupied()
);
//*/
///////////////////////////////////////////////////////////////////////
// frontend assignments
///////////////////////////////////////////////////////////////////////
wire [31:0] debug_radio;
wire [31:0] fe_atr1, fe_atr2;
assign {tx_enable1, SFDX1_RX, SFDX1_TX, SRX1_RX, SRX1_TX, LED_RX1, LED_TXRX1_RX, LED_TXRX1_TX} = fe_atr1[7:0];
assign {tx_enable2, SFDX2_RX, SFDX2_TX, SRX2_RX, SRX2_TX, LED_RX2, LED_TXRX2_RX, LED_TXRX2_TX} = fe_atr2[7:0];
@@ -237,7 +231,8 @@ module b200 (
///////////////////////////////////////////////////////////////////////
// b200 core
///////////////////////////////////////////////////////////////////////
b200_core #(.EXTRA_BUFF_SIZE(12)) b200_xfusion_core
b200_core #(.EXTRA_BUFF_SIZE(12)) b200_core
(
.bus_clk(bus_clk), .bus_rst(bus_rst),
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
@@ -253,15 +248,19 @@ module b200 (
.rxd(gps_txd), .txd(gps_rxd),
.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs)
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs),
.debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6),
.debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0),
.debug()
);
///////////////////////////////////////////////////////////////////////
// GPIF2
///////////////////////////////////////////////////////////////////////
wire [31:0] debug_gpif;
gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(14), .DATA_TX_FIFO_SIZE(14)) slave_fifo32
gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(14), .DATA_TX_FIFO_SIZE(14)) slave_fifo32
(
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_enb(1'b1),
.gpif_ctl({GPIF_CTL8, GPIF_CTL6, GPIF_CTL5, GPIF_CTL4}), .fifoadr({GPIF_CTL11,GPIF_CTL12}),
@@ -274,13 +273,12 @@ module b200 (
.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
.debug(debug_gpif)
.debug()
);
///////////////////////////////////////////////////////////////////////
// Debug port
///////////////////////////////////////////////////////////////////////
assign debug_clk_int = { 1'b0, 1'b0 };
assign debug = 32'b0;
assign debug = 0;
endmodule // B200
top/b200/b200_core.v
+75 -11
View File
@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
/***********************************************************
* B200 Core Guts
@@ -15,7 +27,10 @@ module b200_core
parameter R0_DATA_SID = 8'h50,
parameter R1_DATA_SID = 8'h60,
parameter DEMUX_SID_MASK = 8'hf0,
parameter EXTRA_BUFF_SIZE = 0
parameter EXTRA_BUFF_SIZE = 0,
parameter RADIO_FIFO_SIZE = 12,
parameter SAMPLE_FIFO_SIZE = 11
)
(
////////////////////////////////////////////////////////////////////
@@ -53,8 +68,15 @@ module b200_core
output [7:0] sen, output sclk, output mosi, input miso,
input [31:0] rb_misc,
output [31:0] misc_outs,
output [31:0] debug
////////////////////////////////////////////////////////////////////
// debug UART
////////////////////////////////////////////////////////////////////
output debug_txd, input debug_rxd,
input debug_scl, input debug_sda,
////////////////////////////////////////////////////////////////////
// debug signals
////////////////////////////////////////////////////////////////////
output [63:0] debug
);
localparam SR_CORE_SPI = 8'd8;
localparam SR_CORE_MISC = 8'd16;
@@ -62,7 +84,7 @@ module b200_core
localparam SR_CORE_READBACK = 8'd32;
localparam SR_CORE_GPSDO_ST = 8'd40;
localparam SR_CORE_PPS_SEL = 8'd48;
localparam COMPAT_MAJOR = 16'h0002;
localparam COMPAT_MAJOR = 16'h0003;
localparam COMPAT_MINOR = 16'h0000;
/*******************************************************************
@@ -119,14 +141,14 @@ module b200_core
******************************************************************/
wire [63:0] u0i_ctrl_tdata; wire u0i_ctrl_tlast, u0i_ctrl_tvalid, u0i_ctrl_tready;
axi_fifo #(.WIDTH(65), .SIZE(0)) ushart_timing_fifo
axi_fifo #(.WIDTH(65), .SIZE(0)) uart_timing_fifo
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({u0_ctrl_tlast, u0_ctrl_tdata}), .i_tvalid(u0_ctrl_tvalid), .i_tready(u0_ctrl_tready), .space(),
.o_tdata({u0i_ctrl_tlast, u0i_ctrl_tdata}), .o_tvalid(u0i_ctrl_tvalid), .o_tready(u0i_ctrl_tready), .occupied()
);
cvita_uart #(.SIZE(7)) ushart
cvita_uart #(.SIZE(7)) uart
(
.clk(bus_clk), .rst(bus_rst), .rxd(rxd), .txd(txd),
.i_tdata(u0i_ctrl_tdata), .i_tlast(u0i_ctrl_tlast), .i_tvalid(u0i_ctrl_tvalid), .i_tready(u0i_ctrl_tready),
@@ -247,7 +269,9 @@ module b200_core
/*******************************************************************
* Radio 0
******************************************************************/
radio_b200 #(.FIFO_SIZE(13)) the_radio
wire [63:0] radio0_debug;
radio_b200 #(.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) radio_0
(
.radio_clk(radio_clk), .radio_rst(radio_rst),
.rx(rx0), .tx(tx0), .fe_atr(fe_atr0), .pps(pps),
@@ -258,7 +282,7 @@ module b200_core
.ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready),
.resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready),
.debug()
.debug(radio0_debug)
);
/*******************************************************************
@@ -267,7 +291,7 @@ module b200_core
`ifdef B200_CAN_HAZ_R1
assign radio_st = 8'h2;
radio_b200 #(.FIFO_SIZE(13)) the_radio_1
radio_b200 #(.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) radio_1
(
.radio_clk(radio_clk), .radio_rst(radio_rst),
.rx(rx1), .tx(tx1), .fe_atr(fe_atr1), .pps(pps),
@@ -300,6 +324,46 @@ module b200_core
assign r1_rx_tvalid = r1_tx_tvalid;
assign r1_tx_tready = r1_tx_tready;
`endif
`endif // !`ifdef B200_CAN_HAZ_R1
/*******************************************************************
* Debug UART for FX3
******************************************************************/
wire debug_stb;
wire [31:0] debug_data;
wire [7:0] debug_addr;
serial_to_settings serial_to_settings_i1
(
.clk(bus_clk),
.reset(bus_rst),
.scl(debug_scl),
.sda(debug_sda),
.set_stb(debug_stb),
.set_addr(debug_addr),
.set_data(debug_data)
);
simple_uart debug_uart
(
.clk_i(bus_clk),
.rst_i(bus_rst),
.we_i(debug_stb),
.stb_i(debug_stb),
.cyc_i(debug_stb),
.ack_o(),
.adr_i(debug_addr[2:0]),
.dat_i(debug_data[31:0]),
.dat_o(),
.rx_int_o(),
.tx_int_o(),
.tx_o(debug_txd),
.rx_i(debug_rxd),
.baud_o()
);
endmodule // b200_core
top/b200/b200_tb.v
+213
View File
@@ -0,0 +1,213 @@
module b200_tb ();
wire cat_ce;
wire cat_miso;
wire cat_mosi;
wire cat_sclk;
wire fx3_ce;
wire fx3_miso;
wire fx3_mosi;
wire fx3_sclk;
wire pll_ce;
wire pll_mosi;
wire pll_sclk;
// UART
wire FPGA_RXD0;
wire FPGA_TXD0;
// Catalina Controls
wire codec_enable;
wire codec_en_agc;
wire codec_reset;
wire codec_sync;
wire codec_txrx;
wire [3:0] codec_ctrl_in; // These should be outputs
wire [7:0] codec_ctrl_out; // MUST BE INPUT
// Catalina Data
wire codec_data_clk_p; // Clock from CAT (RX)
wire codec_fb_clk_p; // Clock to CAT (TX)
wire [11:0] rx_codec_d;
wire [11:0] tx_codec_d;
wire rx_frame_p;
wire tx_frame_p;
wire cat_clkout_fpga;
//always on 40MHz clock
wire codec_main_clk_p;
wire codec_main_clk_n;
// Debug Bus
wire [31:0] debug;
wire [1:0] debug_clk;
// GPIF; FX3 Slave FIFO
wire IFCLK; // pclk
wire FX3_EXTINT;
wire GPIF_CTL0; // n_slcs
wire GPIF_CTL1; // n_slwr
wire GPIF_CTL2; // n_sloe
wire GPIF_CTL3; // n_slrd
wire GPIF_CTL7; // n_pktend
wire GPIF_CTL4; // slfifo_flags[0]
wire GPIF_CTL5; // slfifo_flags[1]
wire GPIF_CTL6; // slfifo_flags[2]
wire GPIF_CTL8; // slfifo_flags[3]
wire GPIF_CTL11; // slfifo_addr[1]
wire GPIF_CTL12; // slfifo_addr[0]
wire [31:0] GPIF_D;
wire GPIF_CTL9; // global_reset
// GPS
wire gps_lock;
wire gps_rxd;
wire gps_txd;
wire gps_txd_nmea;
// LEDS
wire LED_RX1;
wire LED_RX2;
wire LED_TXRX1_RX;
wire LED_TXRX1_TX;
wire LED_TXRX2_RX;
wire LED_TXRX2_TX;
// Misc Hardware Control
wire ref_sel;
wire pll_lock;
wire FPGA_CFG_CS; // Driven by FX3 gpio.
wire AUX_PWR_ON; // Driven by FX3 gpio.
// PPS
wire PPS_IN_EXT;
wire PPS_IN_INT;
// RF Hardware Control
wire SFDX1_RX;
wire SFDX1_TX;
wire SFDX2_RX;
wire SFDX2_TX;
wire SRX1_RX;
wire SRX1_TX;
wire SRX2_RX;
wire SRX2_TX;
wire tx_bandsel_a;
wire tx_bandsel_b;
wire tx_enable1;
wire tx_enable2;
wire rx_bandsel_a;
wire rx_bandsel_b;
wire rx_bandsel_c;
b200 b200_i1(
// SPI Interfaces
.cat_ce(),
.cat_miso(),
.cat_mosi(),
.cat_sclk(),
.fx3_ce(),
.fx3_miso(),
.fx3_mosi(),
.fx3_sclk(),
.pll_ce(),
.pll_mosi(),
.pll_sclk(),
// UART
.FPGA_RXD0(),
.FPGA_TXD0(),
// Catalina Controls
.codec_enable(),
.codec_en_agc(),
.codec_reset(),
.codec_sync(),
.codec_txrx(),
.codec_ctrl_in(), // These should be outputs
.codec_ctrl_out(), // MUST BE INPUT
// Catalina Data
.codec_data_clk_p(), // Clock from CAT (RX)
.codec_fb_clk_p(), // Clock to CAT (TX)
.rx_codec_d(),
.tx_codec_d(),
.rx_frame_p(),
.tx_frame_p(),
.cat_clkout_fpga(),
//always on 40MHz clock
.codec_main_clk_p(),
.codec_main_clk_n(),
// Debug Bus
.debug(),
.debug_clk(),
// GPIF, FX3 Slave FIFO
.IFCLK(), // pclk
.FX3_EXTINT(),
.GPIF_CTL0(), // n_slcs
.GPIF_CTL1(), // n_slwr
.GPIF_CTL2(), // n_sloe
.GPIF_CTL3(), // n_slrd
.GPIF_CTL7(), // n_pktend
.GPIF_CTL4(), // slfifo_flags[0]
.GPIF_CTL5(), // slfifo_flags[1]
.GPIF_CTL6(), // slfifo_flags[2]
.GPIF_CTL8(), // slfifo_flags[3]
.GPIF_CTL11(), // slfifo_addr[1]
.GPIF_CTL12(), // slfifo_addr[0]
.GPIF_D(),
.GPIF_CTL9(), // global_reset
// GPS
.gps_lock(),
.gps_rxd(),
.gps_txd(),
.gps_txd_nmea(),
// LEDS
.LED_RX1(),
.LED_RX2(),
.LED_TXRX1_RX(),
.LED_TXRX1_TX(),
.LED_TXRX2_RX(),
.LED_TXRX2_TX(),
// Misc Hardware Control
.ref_sel(),
.pll_lock(),
.FPGA_CFG_CS(), // Driven by FX3 gpio.
.AUX_PWR_ON(), // Driven by FX3 gpio.
// PPS
.PPS_IN_EXT(),
.PPS_IN_INT(),
// RF Hardware Control
.SFDX1_RX(),
.SFDX1_TX(),
.SFDX2_RX(),
.SFDX2_TX(),
.SRX1_RX(),
.SRX1_TX(),
.SRX2_RX(),
.SRX2_TX(),
.tx_bandsel_a(),
.tx_bandsel_b(),
.tx_enable1(),
.tx_enable2(),
.rx_bandsel_a(),
.rx_bandsel_b(),
.rx_bandsel_c()
);
endmodule // b200_tb
top/b200/coregen/chipscope_icon.asy
-4
View File
@@ -6,8 +6,4 @@ LINE Wide 576 112 544 112
PIN 576 112 RIGHT 36
PINATTR PinName control0[35:0]
PINATTR Polarity BOTH
LINE Wide 576 144 544 144
PIN 576 144 RIGHT 36
PINATTR PinName control1[35:0]
PINATTR Polarity BOTH
top/b200/coregen/chipscope_icon.ngc
+1 -1
View File
File diff suppressed because one or more lines are too long
top/b200/coregen/chipscope_icon.v
+2 -4
View File
@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.v
// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 17:04:59 PDT 2013
// \ \ / \
// \___\/\___\
//
@@ -19,11 +19,9 @@
`timescale 1ns/1ps
module chipscope_icon(
CONTROL0,
CONTROL1) /* synthesis syn_black_box syn_noprune=1 */;
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL0;
inout [35 : 0] CONTROL1;
endmodule
top/b200/coregen/chipscope_icon.veo
+2 -3
View File
@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.veo
// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 17:05:00 PDT 2013
// \ \ / \
// \___\/\___\
//
@@ -21,8 +21,7 @@
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_icon YourInstanceName (
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/b200/coregen/chipscope_icon.xco
+4 -4
View File
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Mar 8 19:51:09 2013
# Date: Wed Oct 23 00:04:31 2013
#
##############################################################
#
@@ -30,7 +30,7 @@ SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
@@ -43,7 +43,7 @@ CSET component_name=chipscope_icon
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=2
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
@@ -53,4 +53,4 @@ CSET user_scan_chain=USER1
MISC pkg_timestamp=2012-12-18T02:47:25Z
# END Extra information
GENERATE
# CRC: 865957ec
# CRC: 5ccf4baf
top/b200/coregen/chipscope_icon.xise
+2 -2
View File
@@ -51,8 +51,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:51:40" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BD46AAD29AD5653980780005171DAA9E" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-10-22T17:05:01" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="154D57BA825522169EAB357B0FF9F497" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
top/b200/coregen/chipscope_icon_readme.txt
+1 -1
View File
@@ -1,5 +1,5 @@
The following files were generated for 'chipscope_icon' in directory
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
/home/ianb/fpgadev/usrp3/top/b200/coregen/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
top/b200/coregen/chipscope_ila_128.cdc
+1 -1
View File
@@ -1,5 +1,5 @@
#ChipScope Core Generator Project File Version 3.0
#Fri Mar 08 11:53:53 PST 2013
#Tue Oct 22 15:45:46 PDT 2013
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
SignalExport.bus<0000>.name=TRIG0
SignalExport.bus<0000>.offset=0.0
top/b200/coregen/chipscope_ila_128.ngc
+1 -1
View File
File diff suppressed because one or more lines are too long
top/b200/coregen/chipscope_ila_128.v
+1 -1
View File
@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila_128.v
// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
// \ \ / \
// \___\/\___\
//
top/b200/coregen/chipscope_ila_128.veo
+1 -1
View File
@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila_128.veo
// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
// \ \ / \
// \___\/\___\
//
top/b200/coregen/chipscope_ila_128.xco
+4 -4
View File
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Mar 8 19:52:17 2013
# Date: Tue Oct 22 22:44:09 2013
#
##############################################################
#
@@ -30,7 +30,7 @@ SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
@@ -112,7 +112,7 @@ CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET max_sequence_levels=2
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
@@ -138,4 +138,4 @@ CSET use_rpms=false
MISC pkg_timestamp=2012-12-18T02:47:40Z
# END Extra information
GENERATE
# CRC: 194c140a
# CRC: e17f8549
top/b200/coregen/chipscope_ila_128.xise
+4 -4
View File
@@ -17,11 +17,11 @@
<files>
<file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="chipscope_ila_128.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
@@ -51,8 +51,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_128" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:53:54" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9340B6BAD141C451B74411D3998AD5A4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-10-22T15:45:48" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7648BEB3D1E056005214224EBE9A99B3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
top/b200/coregen/chipscope_ila_128_readme.txt
+1 -1
View File
@@ -1,5 +1,5 @@
The following files were generated for 'chipscope_ila_128' in directory
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
/home/ianb/fpgadev/usrp3/top/b200/coregen/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
top/b200/coregen/coregen.cgp
+1 -2
View File
@@ -1,10 +1,9 @@
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx75
SET device = xc6slx150
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET package = fgg484
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
top/b200/radio_b200.v
+22 -54
View File
@@ -1,14 +1,27 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// radio top level module for b200
// Contains all clock-rate DSP components, all radio and hardware controls and settings
module radio_b200
#(
parameter FIFO_SIZE = 13
parameter RADIO_FIFO_SIZE = 13,
parameter SAMPLE_FIFO_SIZE = 11
)
(input radio_clk, input radio_rst,
input [31:0] rx, output [31:0] tx,
@@ -20,7 +33,7 @@ module radio_b200
input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
output [31:0] debug
output [63:0] debug
);
// ///////////////////////////////////////////////////////////////////////////////
@@ -66,7 +79,7 @@ module radio_b200
.i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}),
.o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) tx_fifo
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) tx_fifo
(.reset(bus_rst),
.i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}),
.o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r}));
@@ -76,7 +89,7 @@ module radio_b200
.i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}),
.o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) rx_fifo
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo
(.reset(radio_rst),
.i_aclk(radio_clk), .i_tvalid(rx_mux_tvalid_r), .i_tready(rx_mux_tready_r), .i_tdata({rx_mux_tlast_r, rx_mux_tdata_r}),
.o_aclk(bus_clk), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .o_tdata({rx_tlast, rx_tdata}));
@@ -162,6 +175,8 @@ module radio_b200
wire [31:0] sid;
wire [23:0] tx_fe_i, tx_fe_q;
wire [31:0] debug_tx_control;
assign tx[31:16] = (run_tx)? tx_fe_i[23:8] : tx_idle[31:16];
assign tx[15:0] = (run_tx)? tx_fe_q[23:8] : tx_idle[15:0];
@@ -180,7 +195,7 @@ module radio_b200
.seqnum(seqnum), .error_code(error_code), .sid(sid),
.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.debug());
.debug(debug_tx_control));
tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
@@ -213,7 +228,7 @@ module radio_b200
wire [11:0] rx_seqnum;
wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i;
new_rx_framer #(.BASE(SR_RX_CTRL+4)) new_rx_framer
new_rx_framer #(.BASE(SR_RX_CTRL+4),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) new_rx_framer
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.vita_time(vita_time),
@@ -266,53 +281,6 @@ module radio_b200
.i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
.o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r));
wire [255:0] debug1;
reg [255:0] debug2;
/* -----\/----- EXCLUDED -----\/-----
always @(posedge radio_clk)
debug2 <= debug1;
wire [35:0] CONTROL0,CONTROL1;
chipscope_ila_256 chipscope_ila_256(
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(radio_clk), // IN
.TRIG0(debug2) // IN BUS [31:0]
);
chipscope_ila_32 chipscope_ila_32(
.CONTROL(CONTROL1), // INOUT BUS [35:0]
.CLK(radio_clk), // IN
.TRIG0(32'd0) // IN BUS [31:0]
);
chipscope_icon chipscope_icon(
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
);
assign debug1 = {
debug_tx_framer, // [214:206]
debug_tx_control, // [205:177]
set_data, // [176:145]
set_addr, // [144:137]
set_stb, // [136]
run_tx, // [135]
run_rx, // [134]
tx_tlast, // [133]
tx_tready, // [132]
tx_tvalid, // [131]
ctrl_tlast, // [130]
ctrl_tready, // [129]
ctrl_tvalid, // [128]
tx_tdata, // [127:64]
ctrl_tdata // [63:0]
};
-----/\----- EXCLUDED -----/\----- */
endmodule // radio_b200
top/b200/timing.ucf
+22 -17
View File
@@ -20,21 +20,26 @@ TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
INST "GPIF_*" IOB = TRUE;
#low speed misc output group
INST "SFDX*" TNM = ls_misc_out;
INST "SRX*" TNM = ls_misc_out;
INST "LED_*" TNM = ls_misc_out;
INST "tx_enable*" TNM = ls_misc_out;
INST "tx_bandsel_*" TNM = ls_misc_out;
INST "rx_bandsel_*" TNM = ls_misc_out;
INST "ref_sel" TNM = ls_misc_out;
INST "*_ce" TNM = ls_misc_out;
INST "*_miso" TNM = ls_misc_out;
INST "*_mosi" TNM = ls_misc_out;
INST "*_sclk" TNM = ls_misc_out;
INST "gps_*" TNM = ls_misc_out;
INST "FPGA_*D0" TNM = ls_misc_out;
INST "SFDX*" TNM = radio_misc_out; # Radio Clk domain
INST "SRX*" TNM = radio_misc_out; # Radio Clk domain
INST "LED_*" TNM = radio_misc_out; # Radio Clk domain
INST "tx_enable*" TNM = radio_misc_out; # Radio Clk domain
INST "tx_bandsel_*" TNM = ls_misc_out; # Bus clk domain
INST "rx_bandsel_*" TNM = ls_misc_out; # Bus clk domain
INST "ref_sel" TNM = ls_misc_out; # Bus clk domain
INST "pll_ce" TNM = ls_misc_out; # Bus clk domain
INST "cat_ce" TNM = ls_misc_out; # Bus clk domain + combinatorial
#INST "fx3_miso" TNM = ls_misc_out; # Combinatorial
INST "cat_miso" TNM = ls_misc_out; # Bus clk domain (I)
INST "cat_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial
INST "pll_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial
INST "*_sclk" TNM = ls_misc_out; # Bus clk domain + combinatorial
INST "gps_*" TNM = ls_misc_out; # Bus clk domain
#INST "FPGA_*D0" TNM = ls_misc_out; # UNUSED
#constrain the misc IOs to the clocks
NET "gpif_clk" TNM_NET = "gpif_clk";
TIMESPEC "TS_gpif_clk" = PERIOD "gpif_clk" 10 ns HIGH 50 %;
TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "gpif_clk" RISING;
TIMEGRP "radio_misc_out" OFFSET = OUT 15 ns AFTER "radio_clk" RISING;
#constrain the misc IOs to the bus clock
NET "bus_clk" TNM_NET = "bus_clk";
TIMESPEC "TS_bus_clk" = PERIOD "bus_clk" 10 ns HIGH 50 %;
TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "bus_clk" RISING;
top/python/check_inout.py
+13 -2
View File
@@ -2,8 +2,19 @@
#
# Copyright 2010 Ettus Research LLC
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# Description:
# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes

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