29086f90013aa4a3e2a9425b9807cf956100b764
Original-commit: 4b4365a517938b365af57674a3ab1462432c2c3a
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%