137 lines
3.7 KiB
Verilog
137 lines
3.7 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Short halfband decimator (intended to be followed by another stage)
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// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
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//
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// These taps designed by halfgen4 from ldoolittle:
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// 2 * 131072 * halfgen4(.75/8,2)
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module small_hb_dec
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#(parameter WIDTH=18)
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(input clk,
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input rst,
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input bypass,
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input run,
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input stb_in,
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input [WIDTH-1:0] data_in,
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output reg stb_out,
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output reg [WIDTH-1:0] data_out);
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// Round off inputs to 17 bits because of 18 bit multipliers
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localparam INTWIDTH = 17;
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wire [INTWIDTH-1:0] data_rnd;
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wire stb_rnd;
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round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in
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(.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd));
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reg stb_rnd_d1;
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reg [INTWIDTH-1:0] data_rnd_d1;
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always @(posedge clk) stb_rnd_d1 <= stb_rnd;
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always @(posedge clk) data_rnd_d1 <= data_rnd;
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wire go;
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reg phase, go_d1, go_d2, go_d3, go_d4;
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always @(posedge clk)
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if(rst | ~run)
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phase <= 0;
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else if(stb_rnd_d1)
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phase <= ~phase;
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assign go = stb_rnd_d1 & phase;
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always @(posedge clk)
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if(rst | ~run)
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begin
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go_d1 <= 0;
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go_d2 <= 0;
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go_d3 <= 0;
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go_d4 <= 0;
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end
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else
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begin
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go_d1 <= go;
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go_d2 <= go_d1;
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go_d3 <= go_d2;
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go_d4 <= go_d3;
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end
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wire [17:0] coeff_a = -10690;
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wire [17:0] coeff_b = 75809;
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reg [INTWIDTH-1:0] d1, d2, d3, d4 , d5, d6;
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always @(posedge clk)
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if(stb_rnd_d1 | rst)
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begin
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d1 <= data_rnd_d1;
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d2 <= d1;
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d3 <= d2;
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d4 <= d3;
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d5 <= d4;
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d6 <= d5;
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end
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reg [17:0] sum_a, sum_b, middle, middle_d1;
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always @(posedge clk)
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if(go)
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begin
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sum_a <= {data_rnd_d1[INTWIDTH-1],data_rnd_d1} + {d6[INTWIDTH-1],d6};
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sum_b <= {d2[INTWIDTH-1],d2} + {d4[INTWIDTH-1],d4};
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//middle <= {d3[INTWIDTH-1],d3};
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middle <= {d3,1'b0};
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end
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always @(posedge clk)
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if(go_d1)
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middle_d1 <= middle;
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wire [17:0] sum = go_d1 ? sum_b : sum_a;
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wire [17:0] coeff = go_d1 ? coeff_b : coeff_a;
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wire [35:0] prod;
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MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) );
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localparam ACCWIDTH = 30;
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reg [ACCWIDTH-1:0] accum;
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always @(posedge clk)
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if(rst)
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accum <= 0;
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else if(go_d2)
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accum <= {middle_d1[17],middle_d1[17],middle_d1,{(16+ACCWIDTH-36){1'b0}}} + {prod[35:36-ACCWIDTH]};
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else if(go_d3)
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accum <= accum + {prod[35:36-ACCWIDTH]};
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wire [WIDTH:0] accum_rnd;
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wire [WIDTH-1:0] accum_rnd_clip;
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wire stb_round;
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round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc
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(.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
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clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip (.in(accum_rnd), .out(accum_rnd_clip));
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// Output
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always @(posedge clk)
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begin
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stb_out <= bypass ? stb_in : stb_round;
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data_out <= bypass ? data_in : accum_rnd_clip;
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end
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endmodule // small_hb_dec
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