40 lines
1.1 KiB
Verilog
40 lines
1.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module srl
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#(parameter WIDTH=18)
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(input clk,
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input rst,
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input write,
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input [WIDTH-1:0] in,
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input [3:0] addr,
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output [WIDTH-1:0] out);
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genvar i;
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generate
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for (i=0;i<WIDTH;i=i+1)
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begin : gen_srl
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SRL16E
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srl16e(.Q(out[i]),
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.A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
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.CE(write|rst),.CLK(clk),.D(in[i]));
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end
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endgenerate
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endmodule // srl
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