228 lines
6.3 KiB
Verilog
228 lines
6.3 KiB
Verilog
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module new_rx_framer
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#(
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parameter BASE=0,
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parameter CHIPSCOPE=0,
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parameter SAMPLE_FIFO_SIZE=10
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)
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(input clk, input reset, input clear,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [63:0] vita_time,
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input strobe,
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input [31:0] sample,
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input run,
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input eob,
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output full,
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output reg [11:0] seqnum,
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output [31:0] sid,
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output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
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output [31:0] debug
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);
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reg [15:0] len;
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reg [63:0] hold_time;
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wire [63:0] dfifo_tdata;
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wire dfifo_tlast, dfifo_tvalid, dfifo_tready;
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wire [80:0] hfifo_tdata;
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wire hfifo_tvalid, hfifo_tready;
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wire [63:0] o_tdata_int;
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wire o_tlast_int, o_tvalid_int, o_tready_int;
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wire [15:0] sample_space;
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wire [15:0] maxlen;
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reg [31:0] holding;
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// FIXME need to handle case where hdr fifo is full (i.e. too many tiny packets)
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assign full = (sample_space == 16'd0) | (sample_space == 16'd1) | ~hdr_tready;
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setting_reg #(.my_addr(BASE), .width(16)) sr_maxlen
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(maxlen),.changed());
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wire sid_changed;
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setting_reg #(.my_addr(BASE+1), .width(32)) sr_sid
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(sid),.changed(sid_changed));
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reg [1:0] instate;
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reg [15:0] numsamps;
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reg nearly_eop;
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always @(posedge clk)
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if(reset | clear)
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begin
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instate <= 0;
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numsamps <= 0;
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nearly_eop <= 0;
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end
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else if (run)
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case(instate)
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0 :
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if(strobe)
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if(eop)
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begin
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instate <= 0;
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numsamps <= 0;
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nearly_eop <= 0;
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end
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else
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begin
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instate <= 1;
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numsamps <= numsamps + 1;
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nearly_eop <= (numsamps >= (maxlen-2));
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end
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1 :
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if(strobe)
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if(eop)
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begin
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instate <= 0;
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numsamps <= 0;
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nearly_eop <= 0;
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end
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else
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begin
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instate <= 2;
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numsamps <= numsamps + 1;
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nearly_eop <= (numsamps >= (maxlen-2));
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end
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2 :
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if(strobe)
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if(eop)
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begin
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instate <= 0;
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numsamps <= 0;
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nearly_eop <= 0;
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end
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else
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begin
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instate <= 1;
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numsamps <= numsamps + 1;
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nearly_eop <= (numsamps >= (maxlen-2));
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end
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endcase // case (instate)
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always @(posedge clk)
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if(strobe && run)
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begin
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holding <= sample;
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if(instate == 0)
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hold_time <= vita_time;
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end
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always @(posedge clk)
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if(reset | clear)
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len <= 5;
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else
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if(strobe && run)
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if(sample_tlast)
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len <= 5;
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else
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len <= len + 1;
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always @(posedge clk)
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if(reset | clear | sid_changed)
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seqnum <= 12'd0;
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else
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if(o_tlast_int & o_tvalid_int & o_tready_int)
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seqnum <= seqnum + 12'd1;
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wire eop = eob | nearly_eop | full;
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wire [63:0] sample_tdata = instate == 1 ? {holding, sample} : {sample, 32'h0};
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wire sample_tlast = eop;
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wire sample_tvalid = run & strobe & ( (instate == 1) | eop );
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wire sample_tready;
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wire [80:0] hdr_tdata = {eob,len[13:0],2'b0,(instate == 0) ? vita_time : hold_time};
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wire hdr_tvalid = sample_tlast && sample_tvalid && sample_tready;
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wire hdr_tready;
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axi_fifo #(.WIDTH(65), .SIZE(SAMPLE_FIFO_SIZE)) datafifo
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({sample_tlast,sample_tdata}), .i_tvalid(sample_tvalid), .i_tready(sample_tready),
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.o_tdata({dfifo_tlast,dfifo_tdata}), .o_tvalid(dfifo_tvalid), .o_tready(dfifo_tready),
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.space(sample_space), .occupied());
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axi_fifo_short #(.WIDTH(81)) hdrfifo
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(hdr_tdata), .i_tvalid(hdr_tvalid), .i_tready(hdr_tready),
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.o_tdata(hfifo_tdata), .o_tvalid(hfifo_tvalid), .o_tready(hfifo_tready),
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.space(), .occupied());
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// The output state machine is responsible for forming output packets.
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// Output packets are formed by combining the entries in the header fifo,
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// and the samples in the data fifo. A single entry in the header fifo
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// contains both the compressed header and the 64 bit time stamp.
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reg [1:0] outstate;
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localparam OUT_IDLE = 2'd0;
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localparam OUT_HEAD = 2'd1;
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localparam OUT_TIME = 2'd2;
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localparam OUT_BODY = 2'd3;
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always @(posedge clk)
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if(reset | clear)
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outstate <= OUT_IDLE;
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else
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case(outstate)
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OUT_IDLE :
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if(hfifo_tvalid) //having a header signals a complete packet
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outstate <= OUT_HEAD;
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OUT_HEAD :
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if(o_tvalid_int && o_tready_int)
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outstate <= OUT_TIME;
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OUT_TIME :
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if(o_tvalid_int && o_tready_int)
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outstate <= OUT_BODY;
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OUT_BODY :
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if(o_tvalid_int && o_tready_int && o_tlast_int)
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outstate <= OUT_IDLE;
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endcase // case (outstate)
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//output data mux feeds from single line of header fifo or the data fifo
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assign o_tdata_int = (outstate == OUT_HEAD) ? { 3'b001, hfifo_tdata[80], seqnum, hfifo_tdata[79:64], sid} :
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(outstate == OUT_TIME) ? hfifo_tdata[63:0] : dfifo_tdata;
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//output the last signal from the data fifo
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assign o_tlast_int = (outstate == OUT_BODY) ? dfifo_tlast : 1'b0;
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//output valid connected to data valid in non-IDLE states
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assign o_tvalid_int = (outstate != OUT_IDLE) & dfifo_tvalid;
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//only pop from header fifo on the very last transaction
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assign hfifo_tready = o_tvalid_int && o_tready_int && o_tlast_int;
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//connect data fifo ready with out ready in the BODY state
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assign dfifo_tready = (outstate == OUT_BODY) ? o_tready_int : 1'b0;
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axi_fifo_short #(.WIDTH(65)) output_fifo
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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.o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(), .occupied());
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/* -----\/----- EXCLUDED -----\/-----
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assign debug[3:0] = {instate, outstate};
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assign debug[7:4] = {1'b0, sample_tlast, sample_tvalid, sample_tready};
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assign debug[11:8] = {1'b0, 1'b0, hfifo_tvalid, hfifo_tready};
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assign debug[15:12] = {1'b0, dfifo_tlast, dfifo_tvalid, dfifo_tready};
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assign debug[19:16] = {1'b0, o_tlast_int, o_tvalid_int, o_tready_int};
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-----/\----- EXCLUDED -----/\----- */
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endmodule // new_rx_framer
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