151 lines
3.7 KiB
Verilog
151 lines
3.7 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module chdr_16sc_to_32f
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#(parameter BASE=0)
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( input clk, input reset, input set_stb, input [7:0] set_addr,
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input [31:0] set_data,
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input [63:0] i_tdata,
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input i_tlast,
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input i_tvalid,
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output i_tready,
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output reg [63:0] o_tdata,
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output o_tlast,
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output o_tvalid,
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input o_tready,
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output [31:0] debug
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);
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wire [31:0] s0_real;
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wire [31:0] s0_imag;
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wire [31:0] s1_real;
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wire [31:0] s1_imag;
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wire chdr_has_hdr = 1'b1;
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wire chdr_has_time = i_tdata[61];
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wire chdr_has_tlr = 1'b0;
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//chdr length calculations
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wire [15:0] chdr_header_lines = chdr_has_time? 16:8;
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wire [15:0] samples = ((i_tdata[47:32] - chdr_header_lines) << 1);
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wire [15:0] i_samples = (i_tdata[47:32] - chdr_header_lines);
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wire [15:0] chdr_payload_lines = samples + chdr_header_lines;
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wire set_sid;
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wire [15:0] my_newhome;
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setting_reg #(.my_addr(BASE), .width(17)) new_destination
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(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),.out({set_sid, my_newhome[15:0]}));
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//state machines
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localparam HEADER = 2'd0;//IDLE
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localparam TIME = 2'd1;
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localparam ODD = 2'd2;
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localparam EVEN = 2'd3;
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reg [1:0] state;
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reg end_on_odd;
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always @(posedge clk) begin
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if (reset) begin
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state <= HEADER;
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end_on_odd <= 1'b0;
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end
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else if (o_tready && i_tvalid) case(state)
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HEADER: begin
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state <= (i_tdata[61])? TIME : ODD;
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end_on_odd <= (i_samples[2:1] == 2 || i_samples[2:1] == 1);
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end
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TIME: begin
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state <= (i_tlast)? HEADER: ODD;
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end
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ODD: begin
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state <= (i_tlast & end_on_odd)? HEADER:EVEN;
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end
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EVEN: begin
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state <= (i_tlast) ? HEADER: ODD;
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end
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default: state <= HEADER;
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endcase
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end
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iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
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iq_to_float_imag0 (.in(i_tdata[63:48]), .out(s0_imag[31:0]));
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iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
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iq_to_float_real0 (.in(i_tdata[47:32]), .out(s0_real[31:0]));
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iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
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iq_to_float_imag1 (.in(i_tdata[31:16]), .out(s1_imag[31:0]));
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iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
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iq_to_float_real1 (.in(i_tdata[15:0]), .out(s1_real[31:0]));
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always @(*)
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case(state)
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HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
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set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
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TIME: o_tdata <= i_tdata;
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ODD: o_tdata <= {s0_imag,s0_real};
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EVEN: o_tdata <= {s1_imag,s1_real};
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default : o_tdata = i_tdata;
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endcase
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assign o_tvalid = i_tvalid;
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assign i_tready = o_tready && ((state != ODD) || (i_tlast && end_on_odd));
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assign o_tlast = i_tlast && ((state == EVEN) || (state == ODD && end_on_odd));
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endmodule
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