46 lines
1.4 KiB
Verilog
46 lines
1.4 KiB
Verilog
//
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// USRP2 - Universal Software Radio Peripheral Mk II
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//
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// Copyright (C) 2008 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module cic_strober
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#(parameter WIDTH=8)
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( input clock,
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input reset,
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input enable,
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input [WIDTH-1:0] rate, // Rate should EQUAL to your desired divide ratio, no more -1 BS
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input strobe_fast,
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output wire strobe_slow );
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reg [WIDTH-1:0] counter;
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wire now = (counter==1);
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assign strobe_slow = now && enable && strobe_fast;
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always @(posedge clock)
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if(reset)
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counter <= 0;
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else if (~enable)
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counter <= rate;
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else if(strobe_fast)
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if(now)
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counter <= rate;
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else
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counter <= counter - 1;
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endmodule // cic_strober
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