46 lines
1.4 KiB
Verilog
46 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module acc
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#(parameter IWIDTH=16, OWIDTH=30)
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(input clk,
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input clear,
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input acc,
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input [IWIDTH-1:0] in,
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output reg [OWIDTH-1:0] out);
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wire [OWIDTH-1:0] in_signext;
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sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH))
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acc_signext (.in(in),.out(in_signext));
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// CLEAR & ~ACC --> clears the accumulator
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// CLEAR & ACC --> loads the accumulator
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// ~CLEAR & ACC --> accumulates
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// ~CLEAR & ~ACC --> hold
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wire [OWIDTH-1:0] addend1 = clear ? 0 : out;
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wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext;
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wire [OWIDTH-1:0] sum_int = addend1 + addend2;
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always @(posedge clk)
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out <= sum_int;
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endmodule // acc
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