54 lines
860 B
Verilog
54 lines
860 B
Verilog
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module serial_to_settings_tb();
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reg clk;
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reg reset;
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wire scl;
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wire sda;
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wire set_stb;
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wire [7:0] set_addr;
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wire [31:0] set_data;
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//
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// These registers optionaly used
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// to drive nets through procedural assignments in test bench.
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// These drivers default to tri-stated.
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//
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reg scl_r;
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reg sda_r;
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assign scl = scl_r;
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assign sda = sda_r;
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initial
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begin
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scl_r <= 1'bz;
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sda_r <= 1'bz;
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end
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serial_to_settings serial_to_settings_i
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(
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.clk(clk),
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.reset(reset),
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// Serial signals (async)
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.scl(scl),
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.sda(sda),
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// Settngs bus out
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.set_stb(set_stb),
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.set_addr(set_addr),
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.set_data(set_data)
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);
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//
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// Bring in a simulation script here
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//
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`include "simulation_script.v"
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endmodule |