41 lines
1.1 KiB
Verilog
41 lines
1.1 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module reset_sync
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(input clk,
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input reset_in,
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output reset_out);
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reg reset_int;
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reg reset_out_tmp;
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//synthesis attribute async_reg of reset_out_tmp is "true";
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//synthesis attribute async_reg of reset_int is "true";
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always @(posedge clk or posedge reset_in)
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if(reset_in)
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{reset_out_tmp,reset_int} <= 2'b11;
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else
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{reset_out_tmp,reset_int} <= {reset_int,1'b0};
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assign reset_out = reset_out_tmp;
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endmodule // reset_sync
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