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e320: Swap out liberio for internal Ethernet

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Original-commit: d01e091c4c7ccc323d305580a27754918b02974b
This commit is contained in:
Alex Williams
2020-07-16 10:00:12 -05:00
committed by Aaron Rossetto
parent c33435c1b9
commit 08c24691a9
4 changed files with 579 additions and 567 deletions
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top/e320/dts/dma-common.dtsi
+23 -344
View File
@@ -4,355 +4,34 @@
*/
&fpga_full {
tx_dma0: dma@43CA0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CA0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma1: dma@43CB0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CB0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma2: dma@43CC0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CC0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma3: dma@43CD0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CD0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma4: dma@43CE0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CE0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma5: dma@43CF0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CF0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma0: dma@43C00000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C00000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma1: dma@43C10000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C10000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma2: dma@43C20000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C20000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma3: dma@43C30000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C30000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma4: dma@43C40000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C40000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma5: dma@43C50000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C50000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
nixge_internal: ethernet@40020000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ni,xge-enet-3.00";
reg = <0x40020000 0x4000
0x40030000 0x2000>;
reg-names = "dma", "ctrl";
clocks = <&clkc 15>;
clock-names = "bus_clk";
usrp_rx_dma0: usrp-rx-dma@43c00000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma0 0>;
dma-names = "dma";
port-id = <0>;
interrupts = <0 52 4>, <0 53 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&intc>;
status = "okay";
regmap = <&dma_conf0>;
offset = <0x0>;
phy-mode = "internal";
local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
usrp_rx_dma1: usrp-rx-dma@43c10000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma1 0>;
dma-names = "dma";
port-id = <1>;
regmap = <&dma_conf0>;
offset = <0x4>;
};
usrp_rx_dma2: usrp-rx-dma@43c20000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma2 0>;
dma-names = "dma";
port-id = <2>;
regmap = <&dma_conf0>;
offset = <0x8>;
};
usrp_rx_dma3: usrp-rx-dma@43c30000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma3 0>;
dma-names = "dma";
port-id = <3>;
regmap = <&dma_conf0>;
offset = <0xc>;
};
usrp_rx_dma4: usrp-rx-dma@43c40000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma4 0>;
dma-names = "dma";
port-id = <4>;
regmap = <&dma_conf0>;
offset = <0x10>;
};
usrp_rx_dma5: usrp-rx-dma@43c50000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma5 0>;
dma-names = "dma";
port-id = <5>;
regmap = <&dma_conf0>;
offset = <0x14>;
};
usrp_tx_dma0: usrp-tx-dma@43ca0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma0 0>;
dma-names = "dma";
port-id = <0>;
};
usrp_tx_dma1: usrp-tx-dma@43cb0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma1 0>;
dma-names = "dma";
port-id = <1>;
};
usrp_tx_dma2: usrp-tx-dma@43cc0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma2 0>;
dma-names = "dma";
port-id = <2>;
status = "okay";
};
usrp_tx_dma3: usrp-tx-dma@43cd0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma3 0>;
dma-names = "dma";
port-id = <3>;
};
usrp_tx_dma4: usrp-tx-dma@43ce0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma4 0>;
dma-names = "dma";
port-id = <4>;
status = "okay";
};
usrp_tx_dma5: usrp-tx-dma@43cf0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma5 0>;
dma-names = "dma";
port-id = <5>;
};
dma_conf0: dma_conf0@42080000 {
compatible = "syscon";
reg = <0x42080000 0x1000>;
uio@40032000 {
compatible = "usrp-uio";
reg = <0x40032000 0x2000>;
reg-names = "misc-enet-int-regs";
status = "okay";
};
};
top/e320/e320.v
+141 -31
View File
@@ -297,25 +297,51 @@ module e320 (
wire [1:0] m_axi_eth_dma_bresp;
wire [1:0] m_axi_eth_dma_rresp;
wire [31:0] m_axi_eth_dma_rdata;
wire m_axi_eth_internal_arvalid;
wire m_axi_eth_internal_awvalid;
wire m_axi_eth_internal_bready;
wire m_axi_eth_internal_rready;
wire m_axi_eth_internal_wvalid;
wire [31:0] m_axi_eth_internal_araddr;
wire [31:0] m_axi_eth_internal_awaddr;
wire [31:0] m_axi_eth_internal_wdata;
wire [3:0] m_axi_eth_internal_wstrb;
wire m_axi_eth_internal_arready;
wire m_axi_eth_internal_awready;
wire m_axi_eth_internal_bvalid;
wire m_axi_eth_internal_rvalid;
wire m_axi_eth_internal_wready;
wire [1:0] m_axi_eth_internal_bresp;
wire [1:0] m_axi_eth_internal_rresp;
wire [31:0] m_axi_eth_internal_rdata;
// Processing System
wire [15:0] IRQ_F2P;
// DMA xport adapter to PS
// Internal Ethernet xport adapter to PS
wire [63:0] h2e_tdata;
wire [7:0] h2e_tkeep;
wire h2e_tlast;
wire h2e_tready;
wire h2e_tvalid;
wire [63:0] e2h_tdata;
wire [7:0] e2h_tkeep;
wire e2h_tlast;
wire e2h_tready;
wire e2h_tvalid;
wire [63:0] m_axis_dma_tdata;
wire [3:0] m_axis_dma_tuser;
wire m_axis_dma_tlast;
wire m_axis_dma_tready;
wire m_axis_dma_tvalid;
wire [63:0] s_axis_dma_tdata;
wire [3:0] s_axis_dma_tdest;
wire s_axis_dma_tlast;
wire s_axis_dma_tready;
wire s_axis_dma_tvalid;
// HP0 -- High Performance port 0
wire [5:0] s_axi_hp0_awid;
wire [31:0] s_axi_hp0_awaddr;
wire [2:0] s_axi_hp0_awprot;
wire s_axi_hp0_awvalid;
@@ -327,7 +353,6 @@ module e320 (
wire [1:0] s_axi_hp0_bresp;
wire s_axi_hp0_bvalid;
wire s_axi_hp0_bready;
wire [5:0] s_axi_hp0_arid;
wire [31:0] s_axi_hp0_araddr;
wire [2:0] s_axi_hp0_arprot;
wire s_axi_hp0_arvalid;
@@ -347,7 +372,6 @@ module e320 (
wire [1:0] s_axi_hp0_arburst;
wire [2:0] s_axi_hp0_arsize;
wire [4:0] s_axi_eth_descriptor_awid;
wire [31:0] s_axi_eth_descriptor_awaddr;
wire [2:0] s_axi_eth_descriptor_awprot;
wire s_axi_eth_descriptor_awvalid;
@@ -359,7 +383,6 @@ module e320 (
wire [1:0] s_axi_eth_descriptor_bresp;
wire s_axi_eth_descriptor_bvalid;
wire s_axi_eth_descriptor_bready;
wire [4:0] s_axi_eth_descriptor_arid;
wire [31:0] s_axi_eth_descriptor_araddr;
wire [2:0] s_axi_eth_descriptor_arprot;
wire s_axi_eth_descriptor_arvalid;
@@ -1147,9 +1170,6 @@ module e320 (
assign IRQ_F2P[0] = arm_eth_rx_irq;
assign IRQ_F2P[1] = arm_eth_tx_irq;
assign {s_axi_hp0_awid, s_axi_hp0_arid} = 12'd0;
assign {s_axi_eth_descriptor_awid, s_axi_eth_descriptor_arid} = 10'd0;
axi_eth_dma inst_axi_eth_dma (
.s_axi_lite_aclk(clk40),
.m_axi_sg_aclk(clk40),
@@ -1284,6 +1304,83 @@ module e320 (
.o_tready(arm_eth_rx_tready)
);
/////////////////////////////////////////////////////////////////////
//
// Internal Ethernet Interface
//
//////////////////////////////////////////////////////////////////////
eth_internal #(
.DWIDTH(REG_DWIDTH),
.AWIDTH(REG_AWIDTH),
.PORTNUM(8'd1)
) eth_internal_i (
// Resets
.bus_rst (bus_rst),
// Clocks
.bus_clk (bus_clk),
//Axi-lite
.s_axi_aclk (clk40),
.s_axi_aresetn (clk40_rstn),
.s_axi_awaddr (m_axi_eth_internal_awaddr),
.s_axi_awvalid (m_axi_eth_internal_awvalid),
.s_axi_awready (m_axi_eth_internal_awready),
.s_axi_wdata (m_axi_eth_internal_wdata),
.s_axi_wstrb (m_axi_eth_internal_wstrb),
.s_axi_wvalid (m_axi_eth_internal_wvalid),
.s_axi_wready (m_axi_eth_internal_wready),
.s_axi_bresp (m_axi_eth_internal_bresp),
.s_axi_bvalid (m_axi_eth_internal_bvalid),
.s_axi_bready (m_axi_eth_internal_bready),
.s_axi_araddr (m_axi_eth_internal_araddr),
.s_axi_arvalid (m_axi_eth_internal_arvalid),
.s_axi_arready (m_axi_eth_internal_arready),
.s_axi_rdata (m_axi_eth_internal_rdata),
.s_axi_rresp (m_axi_eth_internal_rresp),
.s_axi_rvalid (m_axi_eth_internal_rvalid),
.s_axi_rready (m_axi_eth_internal_rready),
// Host-Ethernet DMA interface
.e2h_tdata (e2h_tdata),
.e2h_tkeep (e2h_tkeep),
.e2h_tlast (e2h_tlast),
.e2h_tvalid (e2h_tvalid),
.e2h_tready (e2h_tready),
.h2e_tdata (h2e_tdata),
.h2e_tkeep (h2e_tkeep),
.h2e_tlast (h2e_tlast),
.h2e_tvalid (h2e_tvalid),
.h2e_tready (h2e_tready),
// Vita router interface
.e2v_tdata (m_axis_dma_tdata),
.e2v_tlast (m_axis_dma_tlast),
.e2v_tvalid (m_axis_dma_tvalid),
.e2v_tready (m_axis_dma_tready),
.v2e_tdata (s_axis_dma_tdata),
.v2e_tlast (s_axis_dma_tlast),
.v2e_tvalid (s_axis_dma_tvalid),
.v2e_tready (s_axis_dma_tready),
// MISC
.port_info (),
.device_id (device_id),
.link_up (),
.activity ()
);
/////////////////////////////////////////////////////////////////////
//
// PS Connections
@@ -1373,7 +1470,6 @@ module e320 (
.s_axi_eth_descriptor_araddr(s_axi_eth_descriptor_araddr),
.s_axi_eth_descriptor_arburst(s_axi_eth_descriptor_arburst),
.s_axi_eth_descriptor_arcache(s_axi_eth_descriptor_arcache),
.s_axi_eth_descriptor_arid(s_axi_eth_descriptor_arid),
.s_axi_eth_descriptor_arlen(s_axi_eth_descriptor_arlen),
.s_axi_eth_descriptor_arlock(1'b0),
.s_axi_eth_descriptor_arprot(s_axi_eth_descriptor_arprot),
@@ -1384,7 +1480,6 @@ module e320 (
.s_axi_eth_descriptor_awaddr(s_axi_eth_descriptor_awaddr),
.s_axi_eth_descriptor_awburst(s_axi_eth_descriptor_awburst),
.s_axi_eth_descriptor_awcache(s_axi_eth_descriptor_awcache),
.s_axi_eth_descriptor_awid(s_axi_eth_descriptor_awid),
.s_axi_eth_descriptor_awlen(s_axi_eth_descriptor_awlen),
.s_axi_eth_descriptor_awlock(1'b0),
.s_axi_eth_descriptor_awprot(s_axi_eth_descriptor_awprot),
@@ -1392,12 +1487,10 @@ module e320 (
.s_axi_eth_descriptor_awready(s_axi_eth_descriptor_awready),
.s_axi_eth_descriptor_awsize(s_axi_eth_descriptor_awsize),
.s_axi_eth_descriptor_awvalid(s_axi_eth_descriptor_awvalid),
.s_axi_eth_descriptor_bid(),
.s_axi_eth_descriptor_bready(s_axi_eth_descriptor_bready),
.s_axi_eth_descriptor_bresp(s_axi_eth_descriptor_bresp),
.s_axi_eth_descriptor_bvalid(s_axi_eth_descriptor_bvalid),
.s_axi_eth_descriptor_rdata(s_axi_eth_descriptor_rdata),
.s_axi_eth_descriptor_rid(),
.s_axi_eth_descriptor_rlast(s_axi_eth_descriptor_rlast),
.s_axi_eth_descriptor_rready(s_axi_eth_descriptor_rready),
.s_axi_eth_descriptor_rresp(s_axi_eth_descriptor_rresp),
@@ -1414,31 +1507,29 @@ module e320 (
.S_AXI_HP0_araddr(s_axi_hp0_araddr),
.S_AXI_HP0_arburst(s_axi_hp0_arburst),
.S_AXI_HP0_arcache(s_axi_hp0_arcache),
.S_AXI_HP0_arid(s_axi_hp0_arid),
.S_AXI_HP0_arlen(s_axi_hp0_arlen),
.S_AXI_HP0_arlock(1'b0),
.S_AXI_HP0_arprot(s_axi_hp0_arprot),
.S_AXI_HP0_arqos(4'b0),
.S_AXI_HP0_arready(s_axi_hp0_arready),
.S_AXI_HP0_arregion(4'b0),
.S_AXI_HP0_arsize(s_axi_hp0_arsize),
.S_AXI_HP0_arvalid(s_axi_hp0_arvalid),
.S_AXI_HP0_awaddr(s_axi_hp0_awaddr),
.S_AXI_HP0_awburst(s_axi_hp0_awburst),
.S_AXI_HP0_awcache(s_axi_hp0_awcache),
.S_AXI_HP0_awid(s_axi_hp0_awid),
.S_AXI_HP0_awlen(s_axi_hp0_awlen),
.S_AXI_HP0_awlock(1'b0),
.S_AXI_HP0_awprot(s_axi_hp0_awprot),
.S_AXI_HP0_awqos(4'b0),
.S_AXI_HP0_awready(s_axi_hp0_awready),
.S_AXI_HP0_awregion(4'b0),
.S_AXI_HP0_awsize(s_axi_hp0_awsize),
.S_AXI_HP0_awvalid(s_axi_hp0_awvalid),
.S_AXI_HP0_bid(),
.S_AXI_HP0_bready(s_axi_hp0_bready),
.S_AXI_HP0_bresp(s_axi_hp0_bresp),
.S_AXI_HP0_bvalid(s_axi_hp0_bvalid),
.S_AXI_HP0_rdata(s_axi_hp0_rdata),
.S_AXI_HP0_rid(),
.S_AXI_HP0_rlast(s_axi_hp0_rlast),
.S_AXI_HP0_rready(s_axi_hp0_rready),
.S_AXI_HP0_rresp(s_axi_hp0_rresp),
@@ -1448,6 +1539,8 @@ module e320 (
.S_AXI_HP0_wready(s_axi_hp0_wready),
.S_AXI_HP0_wstrb(s_axi_hp0_wstrb),
.S_AXI_HP0_wvalid(s_axi_hp0_wvalid),
// Ethernet DMA engines
.m_axi_eth_dma_araddr(m_axi_eth_dma_araddr),
.m_axi_eth_dma_arprot(),
.m_axi_eth_dma_arready(m_axi_eth_dma_arready),
@@ -1467,6 +1560,25 @@ module e320 (
.m_axi_eth_dma_wready(m_axi_eth_dma_wready),
.m_axi_eth_dma_wstrb(m_axi_eth_dma_wstrb),
.m_axi_eth_dma_wvalid(m_axi_eth_dma_wvalid),
.m_axi_eth_internal_araddr(m_axi_eth_internal_araddr),
.m_axi_eth_internal_arprot(),
.m_axi_eth_internal_arready(m_axi_eth_internal_arready),
.m_axi_eth_internal_arvalid(m_axi_eth_internal_arvalid),
.m_axi_eth_internal_awaddr(m_axi_eth_internal_awaddr),
.m_axi_eth_internal_awprot(),
.m_axi_eth_internal_awready(m_axi_eth_internal_awready),
.m_axi_eth_internal_awvalid(m_axi_eth_internal_awvalid),
.m_axi_eth_internal_bready(m_axi_eth_internal_bready),
.m_axi_eth_internal_bresp(m_axi_eth_internal_bresp),
.m_axi_eth_internal_bvalid(m_axi_eth_internal_bvalid),
.m_axi_eth_internal_rdata(m_axi_eth_internal_rdata),
.m_axi_eth_internal_rready(m_axi_eth_internal_rready),
.m_axi_eth_internal_rresp(m_axi_eth_internal_rresp),
.m_axi_eth_internal_rvalid(m_axi_eth_internal_rvalid),
.m_axi_eth_internal_wdata(m_axi_eth_internal_wdata),
.m_axi_eth_internal_wready(m_axi_eth_internal_wready),
.m_axi_eth_internal_wstrb(m_axi_eth_internal_wstrb),
.m_axi_eth_internal_wvalid(m_axi_eth_internal_wvalid),
// MGT IO Regport
.m_axi_net_araddr(m_axi_net_araddr),
@@ -1523,16 +1635,16 @@ module e320 (
.S_AXI_GP0_ARESETN(clk40_rstn),
// DMA
.s_axis_dma_tdata(s_axis_dma_tdata),
.s_axis_dma_tdest(s_axis_dma_tdest),
.s_axis_dma_tlast(s_axis_dma_tlast),
.s_axis_dma_tready(s_axis_dma_tready),
.s_axis_dma_tvalid(s_axis_dma_tvalid),
.m_axis_dma_tdata(m_axis_dma_tdata),
.m_axis_dma_tuser(m_axis_dma_tuser),
.m_axis_dma_tlast(m_axis_dma_tlast),
.m_axis_dma_tready(m_axis_dma_tready),
.m_axis_dma_tvalid(m_axis_dma_tvalid)
.s_axis_dma_tdata(e2h_tdata),
.s_axis_dma_tkeep(e2h_tkeep),
.s_axis_dma_tlast(e2h_tlast),
.s_axis_dma_tready(e2h_tready),
.s_axis_dma_tvalid(e2h_tvalid),
.m_axis_dma_tdata(h2e_tdata),
.m_axis_dma_tkeep(h2e_tkeep),
.m_axis_dma_tlast(h2e_tlast),
.m_axis_dma_tready(h2e_tready),
.m_axis_dma_tvalid(h2e_tvalid)
);
/////////////////////////////////////////////////////////////////////
@@ -1699,15 +1811,13 @@ module e320 (
.rx(rx_flat),
.tx(tx_flat),
// DMA to PS
// Internal Ethernet DMA to PS
.m_dma_tdata(s_axis_dma_tdata),
.m_dma_tdest(s_axis_dma_tdest),
.m_dma_tlast(s_axis_dma_tlast),
.m_dma_tready(s_axis_dma_tready),
.m_dma_tvalid(s_axis_dma_tvalid),
.s_dma_tdata(m_axis_dma_tdata),
.s_dma_tuser(m_axis_dma_tuser),
.s_dma_tlast(m_axis_dma_tlast),
.s_dma_tready(m_axis_dma_tready),
.s_dma_tvalid(m_axis_dma_tvalid),
top/e320/e320_core.v
+8 -54
View File
@@ -147,13 +147,11 @@ module e320_core #(
// DMA xport adapter to PS
input wire [63:0] s_dma_tdata,
input wire [3:0] s_dma_tuser,
input wire s_dma_tlast,
output wire s_dma_tready,
input wire s_dma_tvalid,
output wire [63:0] m_dma_tdata,
output wire [3:0] m_dma_tdest,
output wire m_dma_tlast,
input wire m_dma_tready,
output wire m_dma_tvalid,
@@ -724,50 +722,6 @@ module e320_core #(
);
/////////////////////////////////////////////////////////////////////////////
//
// DMA Transport Adapter
//
/////////////////////////////////////////////////////////////////////////////
wire [63:0] dmao_tdata;
wire dmao_tlast;
wire dmao_tvalid;
wire dmao_tready;
wire [63:0] dmai_tdata;
wire dmai_tlast;
wire dmai_tvalid;
wire dmai_tready;
liberio_chdr64_adapter #(
.DMA_ID_WIDTH (4)
) dma_xport_adapter (
.clk (bus_clk),
.rst (bus_rst),
.device_id (device_id),
// From DMA engine to core
.s_dma_tdata (s_dma_tdata),
.s_dma_tuser (s_dma_tuser),
.s_dma_tlast (s_dma_tlast),
.s_dma_tvalid (s_dma_tvalid),
.s_dma_tready (s_dma_tready),
// From core to DMA engine
.m_dma_tdata (m_dma_tdata),
.m_dma_tuser (m_dma_tdest),
.m_dma_tlast (m_dma_tlast),
.m_dma_tvalid (m_dma_tvalid),
.m_dma_tready (m_dma_tready),
// CHDR buses
.s_chdr_tdata (dmao_tdata),
.s_chdr_tlast (dmao_tlast),
.s_chdr_tvalid (dmao_tvalid),
.s_chdr_tready (dmao_tready),
.m_chdr_tdata (dmai_tdata),
.m_chdr_tlast (dmai_tlast),
.m_chdr_tvalid (dmai_tvalid),
.m_chdr_tready (dmai_tready)
);
/////////////////////////////////////////////////////////////////////////////
//
// Radio Daughter board and Front End Control
@@ -1059,14 +1013,14 @@ module e320_core #(
.m_eth_tlast (v2e_tlast ),
.m_eth_tvalid (v2e_tvalid),
.m_eth_tready (v2e_tready),
.s_dma_tdata (dmai_tdata),
.s_dma_tlast (dmai_tlast),
.s_dma_tvalid (dmai_tvalid),
.s_dma_tready (dmai_tready),
.m_dma_tdata (dmao_tdata),
.m_dma_tlast (dmao_tlast),
.m_dma_tvalid (dmao_tvalid),
.m_dma_tready (dmao_tready)
.s_dma_tdata (s_dma_tdata),
.s_dma_tlast (s_dma_tlast),
.s_dma_tvalid (s_dma_tvalid),
.s_dma_tready (s_dma_tready),
.m_dma_tdata (m_dma_tdata),
.m_dma_tlast (m_dma_tlast),
.m_dma_tvalid (m_dma_tvalid),
.m_dma_tready (m_dma_tready)
);
//---------------------------------------------------------------------------
top/e320/ip/e320_ps_bd/e320_ps_bd.tcl
+407 -138
View File
@@ -1,6 +1,60 @@
################################################################
# This is a generated script based on design: e320_ps_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source e320_ps_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7z045ffg900-3
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name e320_ps_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
@@ -8,25 +62,215 @@ set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
create_bd_design $design_name
current_bd_design $design_name
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
puts $errMsg
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set scriptDir [file dirname [info script]]
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:axi_protocol_converter:2.1\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
source "$scriptDir/chdr_dma_top.tcl"
# Hierarchical cell: dma
proc create_hier_cell_dma { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_dma() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_DMA_SG
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_dmac
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma
# Create pins
create_bd_pin -dir I bus_clk
create_bd_pin -dir I bus_rstn
create_bd_pin -dir I clk40
create_bd_pin -dir I clk40_rstn
create_bd_pin -dir O rx_irq
create_bd_pin -dir O tx_irq
# Create instance: axi_dma_eth_internal, and set properties
set axi_dma_eth_internal [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_eth_internal ]
set_property -dict [ list \
CONFIG.c_enable_multi_channel {0} \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_m_axi_mm2s_data_width {64} \
CONFIG.c_m_axis_mm2s_tdata_width {64} \
CONFIG.c_mm2s_burst_size {16} \
CONFIG.c_num_mm2s_channels {1} \
CONFIG.c_num_s2mm_channels {1} \
CONFIG.c_s2mm_burst_size {16} \
CONFIG.c_sg_include_stscntrl_strm {0} \
] $axi_dma_eth_internal
# Create instance: axi_protocol_convert_rx, and set properties
set axi_protocol_convert_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_rx ]
set_property -dict [ list \
CONFIG.TRANSLATION_MODE {0} \
] $axi_protocol_convert_rx
# Create instance: axi_protocol_convert_tx, and set properties
set axi_protocol_convert_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_tx ]
set_property -dict [ list \
CONFIG.TRANSLATION_MODE {0} \
] $axi_protocol_convert_tx
# Create interface connections
connect_bd_intf_net -intf_net axi_dma_eth_internal_M_AXIS_MM2S [get_bd_intf_pins m_axis_dma] [get_bd_intf_pins axi_dma_eth_internal/M_AXIS_MM2S]
connect_bd_intf_net -intf_net axi_dma_eth_internal_M_AXI_MM2S [get_bd_intf_pins axi_dma_eth_internal/M_AXI_MM2S] [get_bd_intf_pins axi_protocol_convert_tx/S_AXI]
connect_bd_intf_net -intf_net axi_dma_eth_internal_M_AXI_S2MM [get_bd_intf_pins axi_dma_eth_internal/M_AXI_S2MM] [get_bd_intf_pins axi_protocol_convert_rx/S_AXI]
connect_bd_intf_net -intf_net axi_dma_eth_internal_M_AXI_SG [get_bd_intf_pins M_AXI_DMA_SG] [get_bd_intf_pins axi_dma_eth_internal/M_AXI_SG]
connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins M_AXI_RX_DMA] [get_bd_intf_pins axi_protocol_convert_rx/M_AXI]
connect_bd_intf_net -intf_net axi_protocol_convert_rx1_M_AXI [get_bd_intf_pins M_AXI_TX_DMA] [get_bd_intf_pins axi_protocol_convert_tx/M_AXI]
connect_bd_intf_net -intf_net s_axi_dmac_1 [get_bd_intf_pins s_axi_dmac] [get_bd_intf_pins axi_dma_eth_internal/S_AXI_LITE]
connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_pins s_axis_dma] [get_bd_intf_pins axi_dma_eth_internal/S_AXIS_S2MM]
# Create port connections
connect_bd_net -net axi_dma_eth_internal_mm2s_introut [get_bd_pins tx_irq] [get_bd_pins axi_dma_eth_internal/mm2s_introut]
connect_bd_net -net axi_dma_eth_internal_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/mm2s_prmry_reset_out_n] [get_bd_pins axi_protocol_convert_tx/aresetn]
connect_bd_net -net axi_dma_eth_internal_s2mm_introut [get_bd_pins rx_irq] [get_bd_pins axi_dma_eth_internal/s2mm_introut]
connect_bd_net -net axi_dma_eth_internal_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/s2mm_prmry_reset_out_n] [get_bd_pins axi_protocol_convert_rx/aresetn]
connect_bd_net -net bus_clk_1 [get_bd_pins bus_clk] [get_bd_pins axi_dma_eth_internal/m_axi_mm2s_aclk] [get_bd_pins axi_dma_eth_internal/m_axi_s2mm_aclk] [get_bd_pins axi_dma_eth_internal/m_axi_sg_aclk] [get_bd_pins axi_protocol_convert_rx/aclk] [get_bd_pins axi_protocol_convert_tx/aclk]
connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_dma_eth_internal/s_axi_lite_aclk]
connect_bd_net -net clk40_rstn_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_dma_eth_internal/axi_resetn]
# Restore current instance
current_bd_instance $oldCurInst
}
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
@@ -34,14 +278,14 @@ proc create_root_design { parentCell } {
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
@@ -54,90 +298,9 @@ proc create_root_design { parentCell } {
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ]
set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ]
set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ]
set_property -dict [ list \
CONFIG.HAS_TLAST 1 \
CONFIG.TDATA_NUM_BYTES 8 \
CONFIG.TDEST_WIDTH 4 \
] $s_axis_dma
set m_axi_eth_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_dma ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_WSTRB {1} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_eth_dma
set m_axi_net [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_net ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_WSTRB {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_net
set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_WSTRB {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_xbar
set s_axi_eth_descriptor [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth_descriptor ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {5} \
CONFIG.MAX_BURST_LENGTH {16} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi_eth_descriptor
set S_AXI_HP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
@@ -155,7 +318,7 @@ proc create_root_design { parentCell } {
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {5} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {16} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {1} \
@@ -169,8 +332,127 @@ proc create_root_design { parentCell } {
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S_AXI_HP0
set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ]
set m_axi_eth_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_dma ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_WSTRB {1} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_eth_dma
set m_axi_eth_internal [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_internal ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {31} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_eth_internal
set m_axi_net [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_net ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_WSTRB {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_net
set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_WSTRB {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_xbar
set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ]
set_property -dict [ list \
CONFIG.FREQ_HZ {200000000} \
] $m_axis_dma
set s_axi_eth_descriptor [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth_descriptor ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {16} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi_eth_descriptor
set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ]
set_property -dict [ list \
CONFIG.FREQ_HZ {200000000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {1} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {8} \
CONFIG.TDEST_WIDTH {4} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $s_axis_dma
# Create ports
set DDR_VRN [ create_bd_port -dir IO DDR_VRN ]
set DDR_VRP [ create_bd_port -dir IO DDR_VRP ]
@@ -224,6 +506,7 @@ proc create_root_design { parentCell } {
set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ]
set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk S_AXI_HP0_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {S_AXI_HP0_ARESETN} \
CONFIG.FREQ_HZ {40000000} \
] $S_AXI_HP0_ACLK
set S_AXI_HP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP0_ARESETN ]
@@ -236,29 +519,29 @@ proc create_root_design { parentCell } {
set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ]
set clk40 [ create_bd_port -dir I -type clk clk40 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axi_net:m_axi_xbar:m_axi_eth_dma} \
CONFIG.ASSOCIATED_BUSIF {m_axi_net:m_axi_xbar:m_axi_eth_dma:m_axi_eth_internal} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
# Create instance: axi_interconnect_hp0, and set properties
set axi_interconnect_hp0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp0 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {2} \
] $axi_interconnect_hp0
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
CONFIG.NUM_MI {6} \
CONFIG.NUM_MI {5} \
] $axi_interconnect_0
# Create instance: axi_interconnect_hp0, and set properties
set axi_interconnect_hp0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp0 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {3} \
] $axi_interconnect_hp0
# Create instance: dma
create_hier_cell_dma [current_bd_instance .] dma 6
create_hier_cell_dma [current_bd_instance .] dma
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
@@ -702,22 +985,22 @@ proc create_root_design { parentCell } {
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
connect_bd_intf_net -intf_net s_axi_eth_descriptor_1 [get_bd_intf_ports s_axi_eth_descriptor] [get_bd_intf_pins axi_interconnect_hp0/S01_AXI]
connect_bd_intf_net -intf_net S_AXI_HP0_1 [get_bd_intf_ports S_AXI_HP0] [get_bd_intf_pins axi_interconnect_hp0/S00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_eth_dma] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_net] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports m_axi_xbar] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_interconnect_0/M05_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins dma/s_axi_dmac]
connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports m_axi_eth_internal] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
connect_bd_intf_net -intf_net axi_protocol_converter_hp0_M_AXI [get_bd_intf_pins axi_interconnect_hp0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
connect_bd_intf_net -intf_net dma_M_AXI_DMA_SG [get_bd_intf_pins axi_interconnect_hp0/S02_AXI] [get_bd_intf_pins dma/M_AXI_DMA_SG]
connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2]
connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma]
connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0]
connect_bd_intf_net -intf_net s_axi_regfile_1 [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins dma/s_axi_regfile]
connect_bd_intf_net -intf_net s_axi_rx_dmac_1 [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac]
connect_bd_intf_net -intf_net s_axi_eth_descriptor_1 [get_bd_intf_ports s_axi_eth_descriptor] [get_bd_intf_pins axi_interconnect_hp0/S01_AXI]
connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma]
# Create port connections
connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din]
@@ -731,12 +1014,12 @@ proc create_root_design { parentCell } {
connect_bd_net -net SPI1_SS_I_0_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net S_AXI_GP0_ACLK_1 [get_bd_ports S_AXI_GP0_ACLK] [get_bd_pins axi_interconnect_0/ACLK]
connect_bd_net -net S_AXI_GP0_ARESETN_1 [get_bd_ports S_AXI_GP0_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN]
connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_ports S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins axi_interconnect_hp0/S01_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK]
connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_ports S_AXI_HP0_ARESETN] [get_bd_pins axi_interconnect_hp0/ARESETN] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/S01_ARESETN]
connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk]
connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn]
connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK]
connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn]
connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_ports S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins axi_interconnect_hp0/S01_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK]
connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_ports S_AXI_HP0_ARESETN] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/S01_ARESETN]
connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins axi_interconnect_hp0/ACLK] [get_bd_pins axi_interconnect_hp0/S02_ACLK] [get_bd_pins dma/bus_clk] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK]
connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins axi_interconnect_hp0/ARESETN] [get_bd_pins axi_interconnect_hp0/S02_ARESETN] [get_bd_pins dma/bus_rstn]
connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn]
connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN]
connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP]
connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2]
@@ -774,41 +1057,27 @@ proc create_root_design { parentCell } {
connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout]
# Create address segments
create_bd_addr_seg -range 0x00004000 -offset 0x40020000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_dma_eth_internal/S_AXI_LITE/Reg] SEG_axi_dma_eth_internal_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_dma/Reg] SEG_m_axi_eth_dma_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x40030000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] SEG_m_axi_eth_internal_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x40004000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_net/Reg] SEG_m_axi_net_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg
create_bd_addr_seg -range 0x00001000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs
create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite4
create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite6
create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite8
create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite10
create_bd_addr_seg -range 0x00010000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma5/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite12
create_bd_addr_seg -range 0x00010000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_tx_dmac_0_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_tx_dmac_1_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_tx_dmac_2_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_tx_dmac_3_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_tx_dmac_4_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CF0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_5/s_axi/axi_lite] SEG_axi_tx_dmac_5_axi_lite
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_5/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma5/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_HIGH_OCM] SEG_processing_system7_0_HP1_HIGH_OCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces dma/axi_dma_eth_internal/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_HIGH_OCM] SEG_processing_system7_0_HP2_HIGH_OCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth_descriptor] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM
create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces s_axi_eth_descriptor] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] SEG_processing_system7_0_HP0_HIGH_OCM
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()