Wade Fife f1380e5f33 fpga: e31x: Fix timeout for timekeeper registers ...

Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.


Original-commit: 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67

2020-08-19 12:28:22 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add more CtrlPort constants

2020-08-19 12:28:22 -05:00

sim

fpga: sim: Update PkgEthernet

2020-07-31 13:22:29 -05:00

tools

fpga: tools: RESOLVE_PATH checks for an empty path

2020-07-30 15:00:06 -05:00

top

fpga: e31x: Fix timeout for timekeeper registers

2020-08-19 12:28:22 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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