miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
f1380e5f3384b79f0b12a3266e0f27c18482fe2f
b210-k7-fpga/top
T
History
Wade Fife f1380e5f33 fpga: e31x: Fix timeout for timekeeper registers 
Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.


Original-commit: 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67
2020-08-19 12:28:22 -05:00
..
b2xxmini
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
b200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x
fpga: e31x: Fix timeout for timekeeper registers
2020-08-19 12:28:22 -05:00
e320
fpga: e320: Fix default YAML target to E320_1G
2020-08-17 07:56:30 -05:00
n3xx
n320: Double radio ingress buffer size
2020-08-12 15:17:48 -05:00
python
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300
fpga: remove liberio
2020-07-20 16:01:03 -05:00
Makefile.common
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00