Wade Fife fd113147be fpga: e320: Fix timeout for timekeeper registers ...

This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.


Original-commit: 9c4a23f0a2a2d38ace75e4ab29f6f62f64155d81

2020-08-19 12:28:22 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add more CtrlPort constants

2020-08-19 12:28:22 -05:00

sim

fpga: sim: Update PkgEthernet

2020-07-31 13:22:29 -05:00

tools

fpga: tools: RESOLVE_PATH checks for an empty path

2020-07-30 15:00:06 -05:00

top

fpga: e320: Fix timeout for timekeeper registers

2020-08-19 12:28:22 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%