Wade Fife 066948f87d fpga: lib: Add ctrlport_to_regport bridge ...

Original-commit: 5d9fb234d31fc5a13111c559a91a82e81c2487fc

2020-08-19 12:28:22 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add ctrlport_to_regport bridge

2020-08-19 12:28:22 -05:00

sim

fpga: sim: Update PkgEthernet

2020-07-31 13:22:29 -05:00

tools

fpga: tools: RESOLVE_PATH checks for an empty path

2020-07-30 15:00:06 -05:00

top

fpga: e320: Fix default YAML target to E320_1G

2020-08-17 07:56:30 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%