Wade Fife 15d9d740ef fpga: sim: Fix stream command and status models
This updates PkgChdrBfm to correct some errors when modeling stream
command and stream status packets.

- Fix behavior when CHDR_W = 512
- Fix assertions in read_ctrl()


Original-commit: ccf5d1e0a06bf8d46d7bf6dc33a17e3228a1bff4
2020-08-31 08:16:43 -05:00
S
Description
No description provided
84 MiB
Languages
Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%