miegl/b210-k7-fpga
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Wade Fife bd5d539bc2 fpga: n3xx: Update AXI interconnect address range 
This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: c6bb9924e56664ccb337694f8ef485ba8245edfd
2020-08-28 15:07:38 -05:00
..
b2xxmini
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
b200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x
fpga: e31x: Change RFNoC Ctrl clock to 40 MHz
2020-08-19 12:28:22 -05:00
e320
fpga: e320: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
n3xx
fpga: n3xx: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
python
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300
fpga: remove liberio
2020-07-20 16:01:03 -05:00
Makefile.common
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00