This change causes HLS IP to be exported with a version of 1.0.0
instead of a date code. Due to a bug in Vivado, date codes after
0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting
an explicit revision avoids this issue.
See Xilinx AR 76960 for details.
Original-commit: 51384afc2c5d4db9e2e45d97382edce8c8039b10
Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh
file in the main x400 directory was being used instead of the one
generated by rfnoc_image_builder.
Original-commit: 121b6c560cacfb5deacdee664dd1f32cafef7b3d
Some comments describing data flow direction were wrong. This commit
updates the Mako files and updates the noc_shell modules with newly
generated versions.
Original-commit: 270a7e13c365d05ba04ab44a2f844d96ba15f43b
The I and Q were swapped in sine_tone, which caused confusion and made
the rotation of REG_CARTESIAN clockwise by default. This effectively
made the resulting frequency negative. This PR makes the I and Q order
consistent with RFNoC and fixes the direction of rotation so that a
positive value for REG_PHASE_INC (phase increment) results in a
counter-clockwise rotation, which yields a positive frequency.
Original-commit: 4e6531f30648ede5be8f93fa49fdcd4973b73813
Updates the language in setupenv.sh --help to better reflect that there
are many locations where Vivado is searched.
Original-commit: e64d3e28316f642c1203722b6f5f2af710a7e281
This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to
the location of the UHD "fpga" directory. This allows you to include
files in your out-of-tree modules relative to the FPGA directory. For
example, you could include the library header file rfnoc_chdr_utils.vh
using the following:
`include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
Some simulators may not support `" outside of the context of a `define,
in which case you can do the following:
`define RFNOC_CHDR_UTILS_PATH \
`"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
`include `RFNOC_CHDR_UTILS_PATH
Original-commit: 66267f515802ff3f965fd44e1f0d3097ada7484f
This sets the ARCH and PART_ID environment variables so that the
selected part family is used for simulations by default. This can be
overridden by changing them in the Makefile for the testbench if a
testbench requires a specific part family. Prior to this change, the
default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which
required support for that part to be installed.
Original-commit: c176046dff4941bcec27b0b72e5a68264c4808e5
There were some rare corner cases where the EOB could get lost in the
DUC due to the dds_timed logic not always passing it through as it
should. This resulted in an underflow error message at the end of
transmission.
This commit also fixes an issue where part of the last packet
used a frequency shift of 0 instead of the requested frequency
shift, and an issue where the first few samples of a burst used the
wrong frequency shift value.
Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only.
The TUSER port is built into the IP but was disabled. It is now
enabled and set to 1 bit wide. This has a very small effect on
resource usage and can be left unconnected when not needed.
The dds_freq_tune block was shared by the DUC and DDC. To avoid
affecting the DDC, a new version, dds_freq_tune_duc, is being
added for the DUC to use that has the necessary fixes.
The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP.
This IP has the undesirable behavior that new inputs must be provided
to push previous outputs through the IP. This wrapper hides that
complexity by adding some logic to ensure all data gets pushed through
automatically. This logic uses the TUSER port on the IP.
Finally, a testbench for dds_timed was added.
Original-commit: 77975d108a704ce18ec52b4ee1764381b1893752
PkgComplex adds functions for doing complex arithmetic in SystemVerilog
simulation.
PkgMath provides mathematical operations and constants that aren't
built into SystemVerilog, such as a constant for pi and the function
round().
PkgRandom adds randomization functions beyond what standard Verilog
supports but that don't require any special licenses or simulators.
Original-commit: da4202e6f74796603072aa14544581604e81df02
Updated some comments that still referenced the old CORDIC
implementation, which is no longer used.
Original-commit: 18e5bdfa100a40376147d1a497645345b2a938b1
This change allows assertion errors/failures in ModelSim to be
detected and causes ModelSim to return a non-zero value when such
an assertion error occurs. This allows the return value of ModelSim
to be used to determine whether or not the testbench passed.
Original-commit: 574146ec8909da367c3441189c2877a287892f7e
VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.
Original-commit: b85b796cbc1f897a69ded1f3ecfba8ec92684c11
This updates the existing PART_NAME generation used in simulation
makefiles to work with newer part families by calling
viv_gen_part_id.py to generate the part name needed by Vivado.
Original-commit: 648c70ae758ab1d15c7ec6cbe57672e8c27640cd
This is a list of testbenches that don't work with ModelSim and should
be excluded when running run_testbenches.py.
Original-commit: 6190eca14ec13db7456a059cbd69c93550aa45c7
This adds the MSIM_VIV_COMPLIBDIR environment variable to specify
a non-default location for the compilation libraries.
This also allows a modelsim.ini other than the one in the ModelSim
installation folder to be used. By default, the one in the simulation
libraries compilation directory will be used. This can be changed by
setting MSIM_MODELSIM_INI to the one you want to use, or set it to an
empty string to use the one in the ModelSim installation folder.
Original-commit: 08473776b28a949027ec8cf2596d8d1b438b979b
Run "make ip" in a separate step for each testbench. This allows some
testbenches to work better with ModelSim because it needs IP files that
aren't known until after the IP is generated.
Make run_testbenches.py more log friendly. Add a -l/--logged option for
when the output is being logged. In this case, we don't want to display
elapsed time every second.
Add "Begin TB Log:" and "End TB Log:" to the output to more easily tell
where the output from one testbench ends and another begins.
Use the basedir argument as the base directory in which to search for
testbenches so that a subset of the repo can be easily specified.
Original-commit: 5a4f0470919440819ab71f44fbc6f5f89a671e41
Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.
Original-commit: b0033158a4c520063540881451d8daac91e98714
Change version from a numeric to a string, in order to
differentiate between versions like "1.1" and "1.10".
Original-commit: ca21048bd2f832b20bb36763f76d46b861b697a5
Adds a time_increment port for situations in which the parameter
TIME_INCREMENT can't be used. They offer the same behavior.
Original-commit: f9c97371048bfc69182187e6d8904a01efbe6d79
This pipelines ctrlport_timer to eliminate the long combinational path
caused by the time comparisons. This change also removes the
PRECISION_BITS parameter and converts it to a signal named
time_ignore_bits.
Original-commit: c6035320215f270d7658cfb6195a96a0b84d6aa7
This adds the ability to call BUILD_VIVADO_IP, as before, followed by
REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and
then rebuild the IP with the patched file.
Original-commit: 78315eca698333ad4dc32818e24c7bf6a740c0cb
Per the RFNoC specification, if we set the frequency of flow
control updates to 0 then the input stream will not send flow control
status updates to the output stream handler.
This change makes it so that when the frequency of flow control status
updates is configured to be zero in the FPGA output stream handler
(i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in
chdr_stream_output) then the output stream handler will not use flow
control. That is, chdr_stream_output will not expect stream status
updates and will not restrict output packets.
Original-commit: 184999c54f0f30a7952d4e8560b393730c00e353
The asynchronous feedback loop on the err signal causes X to get stuck
on the sum signal when simulating. This change adds a check for
simulation only to force X to 0 so that unknown inputs get resolved
once the inputs are known.
Also added default values to the ports out and strobe_out, since having
them uninitialized and without reset was causing simulation issues in
other modules. The FPGA will initialize them to 0, so this change makes
the code equivalent to real hardware behavior.
Original-commit: b9f7af5807f73a5ac2612ea42ac2b65c26a3bff2
The always(*) block was never executing in some simulators because
there were no signals on the right-hand side in the block. Changing it
to an initial block ensures it always runs.
Original-commit: 0b965d579e2df962b91dac141eef6668f932e992
This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This
makes the naming consistent with the rest of the build process (which
uses "e310" for all variants of e31x) and fixes an issue in which the
wrong file name was used by rfnoc_image_builder.
Original-commit: bbd43b16e18ef0a0311ddf4635cbd29c4ac3c367
This updates the IO signatures so that all devices and RFNoC blocks use
the same IO signature for the DRAM. This is needed because the IO
signatures must match between the RFNoC blocks and the devices. This
means that some devices have extra bits in the IO signature for the
address, but the extra bits will simply be ignored.
Original-commit: 8f09caaa06725d2364c63ac7cff02f3298895f4a
- Adds test coverage for stream command and status packets
- Cleans up report output during simulation
- Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can
be run directly instead of just chdr_stream_endpoint_all_tb
Original-commit: 97cb396297828f57bba455a275966c58f1abce6e
This updates PkgChdrBfm to correct some errors when modeling stream
command and stream status packets.
- Fix behavior when CHDR_W = 512
- Fix assertions in read_ctrl()
Original-commit: ccf5d1e0a06bf8d46d7bf6dc33a17e3228a1bff4
This changes the behavior of the stream command with the INIT OpCode
such that sending the command with 0 for the values causes no flow
control stream status packets to be sent in response to incoming data.
Original-commit: 7c849afec4dad605ff6f32f7319933f99a4cd1ce
Fixes various synthesis/simulation warnings that were being generated
due to incorrectly sized constants.
Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.
Original-commit: 9c4a23f0a2a2d38ace75e4ab29f6f62f64155d81
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.
Original-commit: e94a209c5b2559348593a6732d694fd49ab59ad0
Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.
Original-commit: 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67
Device was set to e31x, but this is not a valid device type. All e31x
devices use the e310 device type.
Original-commit: 60b76ebb31f9d1672c1b18367346b3fb522e13e9
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.
Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
Thange allows the mux to switch cleanly between packets, if the mux
select input is changed while a packet is in flight.
Original-commit: cee09d96aee51795ba2c6578f75f25f30ea11548
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.
Also cleans up trailing white space.
Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1
The max FFT size was 4096, but we don't currently have any devices that
can do that without modification. This is because, currently, the FFT
size must be the same as the packet size, and the largest packet
size supported by most devices is about 8000 bytes, or 2000
sc16 samples. Therefore, the largest FFT size supported without
modifying other code is 1024 samples.
This change frees up about 21% of the LUTs and 36% of the BRAM used by
axi_fft and makes the software block controller and the IP agree on the
maximum FFT size.
Original-commit: 4f387c8ff0571deedc86dc459e94e555b9768282
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.
Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
Adding a check for bursts that cross the 4 KiB boundary to the AXI4
memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
Original-commit: 24f8bb39fd2769ff93d11b21152a834500152de4
This change fixes the case where CHDR_W < ITEM_W*NIPC.
It also adds a state machine to stall the input to the pyld_fifo to
ensure that the pkt_info_fifo will not overflow. Previously in some
cases it allowed the same word to be inserted into the pyld_fifo
multiple times.
Original-commit: b862eda69cf41c7044a1805324f2fcfef5b0ba3d
This module takes an AXI-Stream without TLAST and outputs the
same AXI-Stream with TLAST based on the provided packet size
input.
Original-commit: b0b3849a18e1f2d3cb255a507b01ac5e7a9416a0
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
Wade Fife