Wade Fife
79add58c25
This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to the location of the UHD "fpga" directory. This allows you to include files in your out-of-tree modules relative to the FPGA directory. For example, you could include the library header file rfnoc_chdr_utils.vh using the following: `include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" Some simulators may not support `" outside of the context of a `define, in which case you can do the following: `define RFNOC_CHDR_UTILS_PATH \ `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" `include `RFNOC_CHDR_UTILS_PATH Original-commit: 66267f515802ff3f965fd44e1f0d3097ada7484f