sim: Update chdr_16sc_to_sc12 testbench
Modified to send 2 packets back to back at each packet size to test output during sequential input packets. Also fixed whitespace. Signed-off-by: michael-west <michael.west@ettus.com> Original-commit: 439770b964be45e6160cf99a0b1551fdd2002fa9
This commit is contained in:
michael-west
committed by
Aaron Rossetto
Aaron Rossetto
parent
946ff5574d
commit
5983927439
+162
-140
@@ -8,163 +8,185 @@
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module chdr_16sc_to_12sc_tb();
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reg clk = 0;
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reg reset = 1;
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//generate clock
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always #10 clk = ~clk;
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reg clk = 0;
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reg reset = 1;
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//generate clock
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always #10 clk = ~clk;
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initial $dumpfile("chdr_16sc_to_12sc_tb.vcd");
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initial $dumpvars(0,chdr_16sc_to_12sc_tb);
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initial $dumpfile("chdr_16sc_to_12sc_tb.vcd");
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initial $dumpvars(0,chdr_16sc_to_12sc_tb);
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//tells when to finish
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initial
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//tells when to finish
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initial
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begin
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#50 reset = 0;
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#50000;
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$finish;
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end
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//setting registers and wire
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reg [63:0] i_tdata;
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reg i_tlast = 0;
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reg i_tvalid = 0;
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wire i_tready ;
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reg [7:0] set_addr;
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reg [31:0] set_data;
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reg set_stb;
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wire [63:0] o_tdata;
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wire o_tlast;
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wire o_tvalid;
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reg o_tready;
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chdr_16sc_to_12sc #(.BASE(89))dut
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(.clk(clk), .reset(reset),
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.set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
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.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
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//if you want to feed a bigger input change array sizes here
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reg [63:0] data[0:7];
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initial $readmemh("from16_to_x.hex", data);
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//test packets loop
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task test_packets;
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input [15:0] len;
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input [31:0] sid;
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reg [1:0] index;
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begin
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#50 reset = 0;
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#50000;
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$finish;
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end
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//setting registers and wire
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reg [63:0] i_tdata;
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reg i_tlast = 0;
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reg i_tvalid = 0;
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wire i_tready ;
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reg [7:0] set_addr;
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reg [31:0] set_data;
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reg set_stb;
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wire [63:0] o_tdata;
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wire o_tlast;
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wire o_tvalid;
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reg o_tready;
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chdr_16sc_to_12sc #(.BASE(89))dut
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(.clk(clk), .reset(reset),
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.set_data(set_data), .set_stb(set_stb), .set_addr(set_addr),
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.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), .debug());
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//if you want to feed a bigger input change array sizes here
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reg [63:0] data[0:7];
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initial $readmemh("from16_to_x.hex", data);
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//test packet loop
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task test_packet;
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input [15:0] len;
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input [31:0] sid;
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reg [1:0] index;
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begin
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index <= 0;
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@(posedge clk) ;
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//send header
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i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
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i_tvalid <= 1;
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i_tlast <= 0;
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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i_tdata <= {64'b0};
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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//-1 for last bit accounting
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repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
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begin
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i_tdata <= {data[index]};
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index <= index+1;
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//while (i_tready != 1)
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//@(posedge clk);
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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end
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i_tlast <= 1'b1;
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i_tdata <= {data[index]};
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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i_tvalid <= 0;
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end
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endtask // test_packet
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//test_destination loop
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task test_destination;
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input enable;
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input [15:0] dest_home;
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begin
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index <= 0;
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//first packet
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@(posedge clk) ;
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//send header
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i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
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i_tvalid <= 1;
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i_tlast <= 0;
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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set_data <= {enable,dest_home};
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set_addr <= 89;
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set_stb <= 1;
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i_tdata <= {64'b0};
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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set_stb <= 0;
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//-1 for last bit accounting
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repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
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begin
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i_tdata <= {data[index]};
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index <= index+1;
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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end
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endtask
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i_tlast <= 1'b1;
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i_tdata <= {data[index]};
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@(posedge clk);
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// second packet
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index <= 0;
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//send header
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i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
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i_tvalid <= 1;
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i_tlast <= 0;
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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i_tdata <= {64'b0};
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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//-1 for last bit accounting
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repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
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begin
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i_tdata <= {data[index]};
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index <= index+1;
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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end
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i_tlast <= 1'b1;
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i_tdata <= {data[index]};
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@(posedge clk);
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while (i_tready != 1)
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@(posedge clk);
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i_tvalid <= 0;
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i_tlast <= 0;
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end
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endtask // test_packet
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//test_destination loop
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task test_destination;
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input enable;
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input [15:0] dest_home;
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begin
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@(posedge clk);
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set_data <= {enable,dest_home};
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set_addr <= 89;
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set_stb <= 1;
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@(posedge clk);
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set_stb <= 0;
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end
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endtask
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//main loop
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initial
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begin
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i_tvalid <= 0;
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o_tready <= 1;
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//main loop
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initial
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begin
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i_tvalid <= 0;
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o_tready <= 1;
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i_tdata <= 0;
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i_tdata <= 0;
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@(negedge reset);
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@(posedge clk);
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@(posedge clk);
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@(negedge reset);
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@(posedge clk);
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@(posedge clk);
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//end on line one
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//1
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test_destination(1,16'hFEED);
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test_packet(4, 32'hDEAD_BEEF);
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//2
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test_destination(1,16'hFEED);
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test_packet(8, 32'hDEAD_BEEF);
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//3
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test_destination(1,16'hFEED);
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test_packet(12, 32'hDEAD_BEEF);
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//4
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//Set SID
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test_destination(1,16'hFEED);
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test_destination(1,16'hFEED);
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test_packet(16, 32'hDEAD_BEEF);
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//5
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test_destination(1,16'hFEED);
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test_packet(20, 32'hDEAD_BEEF);
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//6
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test_destination(1,16'hFEED);
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test_packet(24, 32'hDEAD_BEEF);
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//1 sample
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test_destination(1,16'h1111);
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test_packets(4, 32'hDEAD_BEEF);
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//end on line two
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//2 samples
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test_destination(1,16'h2222);
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test_packets(8, 32'hDEAD_BEEF);
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//7
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//3 samples
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test_destination(1,16'h3333);
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test_packets(12, 32'hDEAD_BEEF);
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test_destination(1,16'hFEED);
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test_packet(28, 32'hDEAD_BEEF);
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//8
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test_destination(1,16'hFEED);
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test_packet(32, 32'hDEAD_BEEF);
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//4 samples
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test_destination(1,16'h4444);
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test_packets(16, 32'hDEAD_BEEF);
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end
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//5 samples
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test_destination(1,16'h5555);
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test_packets(20, 32'hDEAD_BEEF);
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//6 samples
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test_destination(1,16'h6666);
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test_packets(24, 32'hDEAD_BEEF);
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//7 samples
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test_destination(1,16'h7777);
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test_packets(28, 32'hDEAD_BEEF);
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//8 samples
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test_destination(1,16'h8888);
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test_packets(32, 32'hDEAD_BEEF);
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end
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endmodule
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