michael-west 5983927439 sim: Update chdr_16sc_to_sc12 testbench ...

Modified to send 2 packets back to back at each packet size to test
output during sequential input packets.  Also fixed whitespace.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 439770b964be45e6160cf99a0b1551fdd2002fa9

2021-08-10 15:19:32 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

sim: Update chdr_16sc_to_sc12 testbench

2021-08-10 15:19:32 -05:00

sim

fpga: sim: Add PkgComplex, PkgMath, and PkgRandom

2021-08-08 14:59:26 -05:00

tools

fpga: sim: Add PkgComplex, PkgMath, and PkgRandom

2021-08-08 14:59:26 -05:00

top

N3xx: Fix White Rabbit

2021-08-04 15:19:58 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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