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N3xx: Fix White Rabbit

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Reconnect the signals from the White Rabbit module to the TDC in the
FPGA.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: c0637bae1e4a0ddb996cf2b7eadfad22f782874b
This commit is contained in:
michael-west
2021-08-04 15:19:58 -05:00
committed by Aaron Rossetto
parent bb5bff88f6
commit 8164e94fbd
1 changed files with 10 additions and 0 deletions
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top/n3xx/n3xx_mgt_channel_wrapper.v
+10
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@@ -244,6 +244,12 @@ module n3xx_mgt_channel_wrapper #(
wire [LANES-1:0] reg_rd_resp_flat;
wire [(LANES*REG_DWIDTH)-1:0] reg_rd_data_flat;
wire [LANES-1:0] mod_pps_flat;
wire [LANES-1:0] mod_refclk_flat;
// NOTE: Connecting WR signals of first lane only
assign mod_pps = mod_pps_flat[0];
assign mod_refclk = mod_refclk_flat[0];
regport_resp_mux #(
.WIDTH (REG_DWIDTH),
@@ -338,6 +344,10 @@ module n3xx_mgt_channel_wrapper #(
.port_info (port_info[l*32 +: 32]),
.device_id (device_id),
// Timebase Outputs
.mod_pps(mod_pps_flat[l]),
.mod_refclk(mod_refclk_flat[l]),
// Sideband White Rabbit Control
.wr_reset_n (wr_reset_n),
.wr_refclk (wr_refclk),